PRELIMINARY
B9852
High Performance Pentium III Clock Buffer
AC Parameters
133 MHz CPU
100 MHz CPU
Characteristic
Symbol
tpZL, tpZH
tpLZ, tpHZ
Tstable
Units
nS
nS
Notes
Min
1.0
1.0
Max
10.0
10.0
3
Min
1.0
1.0
Max
10.0
10.0
3
Output enable delay (all outputs)
Output disable delay (all outputs)
All clock Stabilization from power-up
mS
4
Notes:
1. Period, jitter, offset and skew measured on rising edge @1.5V.
2. THIGH is measured at 2.4V.
3. TLOW is measured at 0.4V for all outputs.
4. The time specified is measured from when VDD achieves its nominal operating level (typical condition VDD = 3.15V) till the frequency output is
stable and operating within specification.
5. TRISE and TFALL are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.0V JEDEC Specification.
6. The average period over any 1 uS period of time must be greater than the minimum specified period.
7. Calculated at minimum edge-rate (1V/nS) to guarantee 45/55% duty-cycle. Pulsewidth is required to be wider at faster edge-rate to ensure duty-
cycle specification is met.
8. Conditional upon all 66_IN CLK specification being met.
9. Conditional upon all 14.318_IN specification being met.
Group Skew and Jitter Limits
Pin-Pin Skew or
Pair-to-Pair Skew
MAX
Cycle-Cycle
Jitter
350 pS
300 pS
500 pS
1000 pS
Duty Cycle
Nom VDD
Skew, Jitter
Measure Points
Output Group
48 MHz
3V66
N/A
250 pS
500 pS
N/A
45/55
45/55
45/55
45/55
3.3 V
3.3 V
3.3 V
3.3 V
1.5 V
1.5 V*
1.5 V*
1.5 V*
PCI
REF
*Inputs 66_IN and 14.318_IN jitter and duty cycle must be in 45-55% range and less than 200 pS respectively.
Group Offset Limits
Group
3V66 to PCI
Notes:
Offset
Measurement Loads (Lumped) Measure Point
3V66@ 30 pF, PCI @ 30 pF 3V66@ 1.5V, PCI @ 1.5 V
1.5-3.5 nS 3V66 leads
1. All offsets are measured at a 1.5 volt level on their rising edges.
Device Test Mode
This device implements a test mode to enhance board level testing. When this mode is enabled the internal PLL is
bypassed and the clock that is present on the 14.318_IN is divided by 2 and presented on the 48M1 and 48M2 clock
output pins. This function is accessed via the devices SMBUS interface. The feature is enabled by setting Byte 4 Bit 0 to
a logic 0 level.
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07076 Rev. **
5/9/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
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