PRELIMINARY
B9680
SMBUS System Clock Buffer
DC Parameters
Characteristic
Symbol Min
Typ
Max
1.0
-
Units
Conditions
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
VIL1
VIH1
VIL2
VIH2
IIL
-
-
-
-
-
Vdc
Vdc
Vdc
Vdc
µA
Applicable to OE input
2.0
-
1.0
-
Applicable to I²C’s SDATA and SCLK
inputs
2.2
-66
Input Low Current (@VIL =
VSS)
-5
For internal Pull up resistors, Note 1
Input High Current (@VIL =
VDD)
IIH
5
µA
Tri-State leakage Current
Dynamic Supply Current
Ioz
-
-
-
-
10
µA
Idd133
160
mA
Input clock=133MHz, all outputs ON and
w/30pF
Dynamic Supply Current
Idd100
-
-
90
mA
Input clock=100MHz, all outputs ON and
w/30pF
Static Supply Current
Input pin capacitance
Output pin capacitance
Pin Inductance
Isdd
Cin
-
-
-
-
-
-
-
-
400
5
µA
pF
pF
nH
All outputs disabled, no input clock
Cout
Lpin
6
7
VDD = VDDC = 3.3V ±5%, TA = 0ºC to +70ºC
Note 1: Applicable to SDATA, and SCLK inputs. The pull-up resistor has a typical value of 250KΩ, but may vary between 200KΩ to 500KΩ
AC Parameters
Characteristic
Symbol
-
Min
45
-
Typ
50
-
Max
55
Units
%
Conditions
Measured at 1.5V (50/50 in)
Output Duty Cycle
Buffer out/out Skew All
Buffer Outputs
tSKEW
250
pS
30 pF Load Measured at 1.5V
Buffer input to output Delay
Jitter Cycle to Cycle*
tDLY
TJCC
TJabs
1.0
-
5.0
100
150
nS
pS
pS
@ 30 pF loading, 133MHz clock
@ 30 pF loading, 133.3MHz clock
Jitter Absolute (Peak to
Peak)*
VDD=VDDC = 3.3V ±5%, TA = 0ºC to +70ºC
*This jitter is additive to the input clock’s jitter.
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07074 Rev. **
9/15/2000
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
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