PRELIMINARY
B9680
SMBUS System Clock Buffer
Description
Pin Description
PIN
No.
11
Pin
Name
REFIN
PWR
VDD
VDD
I/O
I
TYPE
PAD
This pin is connected to the input reference clock. This clock
must be in the range of 10.0 to 166.6 Mhz.
4,5,8,9,1
3,14,17,1
8,,21,28,
31,32,35,
36,40,41,
44,45
O
BUF1 Low skew output clock
CLK(1:18)
38
-
I
PAD
Buffer Output Enable pin. When forced to a logic low level this
OE
pin is used to place all output clocks (CLK1:18} in a tri state
condition. This feature facilitates in production board level
testing to be easily implemented for the clocks that this device
produces. Has internal pull-up resistor, typically 250KΩ
Serial data of SMBUS 2-wire control interface. Has internal pull-
up resistor, typically 250KΩ
Serial clock of SMBUS 2-wire control interface. Has internal
pull-up resistor, typically 250KΩ
Ground pins for clock output buffers. These pins must be
returned to the same potential to reduce output clock skew.
24
25
VDDC
VDDC
I
I
PAD
PAD
-
SDATA
SDCLK
VSS
6, 10, 15,
19, 22,
27, 30,
34, 39,
43
PWR
3, 7, 12,
16, 20,
29, 33,
37, 42,
46
-
PWR
-
Power for output clock buffers.
VDD
23
26
-
-
PWR
PWR
-
-
Power for core logic.
VDDC
VSSC
Ground supply pins for internal core logic.
No connection.
1,2,47,48
NC
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07074 Rev. **
9/15/2000
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
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