PRELIMINARY
B9680
SMBUS System Clock Buffer
2-Wire SMBUS Control Interface
The 2-wire control interface implements a write only slave interface. The device cannot be read back. Sub-addressing is
not supported, thus all preceding bytes must be sent in order to change one of the control bytes. The 2-wire control
interface allows each clock output to be individually enabled or disabled.
During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK
is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to indicate the
start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer
cycle is a 7-bit address with a Read/Write bit as the LSB. Data is transferred MSB first.
The device will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low) signal on
the SDATA wire following reception of each byte. The device will not respond to any other control interface conditions.
Previously set control registers are retained.
Serial Control Registers
NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true
power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN# pin is activated.
Following the acknowledge of the Address Byte (D2), two additional bytes must be sent:
1) “Command Code “ byte, and
2) “Byte Count” byte.
Although the data (bits) in these two bytes are considered “don’t care”, they must be sent and will be acknowledged.
After the Command Code and the Count bytes have been acknowledged, the below described sequence (Byte
0, Byte 1, Byte 2, ....) will be valid and acknowledged.
Byte 0: Clock Output Select Register (1 = enable, 0 = Stopped, Default=FF)
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
18
17
14
13
9
8
5
4
Description
1
1
1
1
1
1
1
1
CLK8 (Active = 1, Forced low = 0)
CLK7 (Active = 1, Forced low = 0)
CLK6 (Active = 1, Forced low = 0)
CLK5 (Active = 1, Forced low = 0)
CLK4 (Active = 1, Forced low = 0)
CLK3 (Active = 1, Forced low = 0)
CLK2 (Active = 1, Forced low = 0)
CLK1 (Active = 1, Forced low = 0)
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07074 Rev. **
9/15/2000
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
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