PRELIMINARY
B9680
SMBUS System Clock Buffer
Serial Control Registers (Cont.)
Byte 1: Clock Output Register (1 = enable, 0 = Stopped, Default=FF)
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
45
44
41
40
36
35
32
31
Description
1
1
1
1
1
1
1
1
CLK18 (Active = 1, Forced low = 0)
CLK17(Active = 1, Forced low = 0)
CLK16 (Active = 1, Forced low = 0)
CLK15 (Active = 1, Forced low = 0)
CLK14 (Active = 1, Forced low = 0)
CLK13(Active = 1, Forced low = 0)
CLK12 (Active = 1, Forced low = 0)
CLK11 (Active = 1, Forced low = 0)
Byte 2: Clock Output Register (1 = enable, 0 = Stopped, Default=C0)
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
Description
CLK10 (Active = 1, Forced low = 0)
CLK9 (Active = 1, Forced low = 0)
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
1
1
0
0
0
0
0
0
28
21
-
-
-
-
-
-
Maximum Ratings
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Maximum Input Voltage Relative to VSS: VSS - 0.3V
Maximum Input Voltage Relative to VDD:VDD + 0.3V
Storage Temperature:
Operating Temperature:
Maximum ESD protection
Maximum Power Supply:
-65ºC to + 150ºC
0ºC to +85ºC
2KV
5.5V
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07074 Rev. **
9/15/2000
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Page 4 of 10
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