ADVANCE
S27KL0641, S27KS0641
Table 3.1 Command-Address Bit Definitions (Continued)
CA Bit#
Bit Name
Bit Function
Reserved for future column address expansion.
Reserved bits should be set to 0 by the HyperBus master.
15-3
Reserved
Lower Column component of the target address: System word address bits A2-0 selecting the
starting word within a row.
Lower Column
(word) Address
2-0
3.2
Read Transactions
Table 3.2 Maximum Operating Frequency For Latency Code Options
Maximum Operating Frequency
(MHz)
Latency Code
0000
0001
0010
0011
Latency Clocks
5
133
166
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
83
6
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
3
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
4
100
Note:
1. The Latency Code is the value loaded into Configuration Register bits CR0[7:4].
3.3
Write to Memory Space Transactions
When a linear burst write reaches the last address in the array, continuing the burst beyond the last address has undefined results.
Document Number: 001-97964 Rev. *E
Page 6 of 29
CYPRESS [ CYPRESS ]
