ADVANCE
S27KL0641, S27KS0641
2. HyperRAM Product Overview
The HyperRAM Family consists of multiple density option, 1.8V or 3.0V core and I/O, synchronous self-refresh Dynamic RAM
(DRAM) memory devices. This family provides a HyperBus slave interface to the host system. HyperBus has an 8 bit (1 byte) wide
DDR data bus and uses only word-wide (16-bit data) address boundaries. Read transactions provide 16 bits of data during each
clock cycle (8 bits on both clock edges). Write transactions take 16 bits of data from each clock cycle (8 bits on each clock edge).
Figure 2.1 HyperRAM Interface
RESET#
V
CC
V
Q
CC
CS#
CK
DQ[7:0]
RWDS
CK#
V
SS
V
Q
SS
Read and write transactions require two clock cycles to define the target row address and burst type, then an initial access latency of
tACC. During the Command-Address (CA) part of a transaction, the memory will indicate whether an additional latency for a required
refresh time (tRFH) is added to the initial latency; by driving the RWDS signal to the High state. During the CA period the third clock
cycle will specify the target word address within the target row. During a read (or write) transaction, after the initial data value has
been output (or input), additional data can be read from (or written to) the row on subsequent clock cycles in either a wrapped or
linear sequence. When configured in linear burst mode, the device will automatically fetch the next sequential row from the memory
array to support a continuous linear burst. Simultaneously accessing the next row in the array while the read or write data transfer is
in progress, allows for a linear sequential burst operation that can provide a sustained data rate of 333 MB/s (1 byte (8 bit data bus)
* 2 (data clock edges) * 166 MHz = 333 MB/s).
Document Number: 001-97964 Rev. *E
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