ADVANCE
S27KL0641, S27KS0641
1. General Description
The Spansion HyperRAMTM family of products are high-speed CMOS, Self-refresh Dynamic RAM (DRAM) devices, with a HyperBus
interface.
The Random Access Memory (RAM) array uses dynamic cells that require periodic refresh. Refresh control logic within the device
manages the refresh operations on the RAM array when the memory is not being actively read or written by the HyperBus interface
master (host). Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the
memory uses static cells that retain data without refresh. Hence, the memory can also be described as Pseudo Static RAM
(PSRAM).
Because the DRAM cells cannot be refreshed during a read or write transaction, there is a requirement that the host not perform
read or write burst transfers that are long enough to block the necessary internal logic refresh operations when they are needed. The
host is required to limit the duration of transactions and allow additional initial access latency, at the beginning of a new transaction,
if the memory indicates a refresh operation is needed.
HyperBus is a low signal count, Double Data Rate (DDR) interface, that achieves high speed read and write throughput. The DDR
protocol transfers two data bytes per clock cycle on the DQ input/output signals. A read or write transaction on HyperBus consists of
a series of 16-bit wide, one clock cycle data transfers at the internal HyperRAM core with two corresponding 8-bit wide, one-half-
clock-cycle data transfers on the DQ signals. All inputs and outputs are LV-CMOS compatible. Ordering Part Number (OPN) device
versions are available for core (VCC) and IO buffer (VCCQ) supplies of either 1.8V or 3.0V (nominal).
Command, Address, and Data information is transferred over the eight HyperBus DQ signals. The clock is used for information
capture by a HyperBus device when receiving Command-Address/Data on the DQ signals. Command-Address values are center
aligned with clock edges.
The Read/Write Data Strobe (RWDS) is a bidirectional signal that indicates:
– when data will start to transfer from the memory to the host in read transactions (initial read latency),
– when data is being transferred from the memory to the host during read data transfers (source synchronous read data strobe),
– when data will start to transfer from the host to the memory in write transactions (initial write latency),
– and data masking during write data transfers.
During the command and address cycles of a read or write transaction, RWDS acts as an output from the memory to indicate
whether additional initial access latency is needed to perform a dynamic memory refresh operation.
During read data transfers, RWDS is a read data strobe with data values edge aligned with the transitions of RWDS driven by the
memory device.
During write data transfers, RWDS indicates whether a data byte is masked (prevented from changing the byte location in memory)
or not masked (written to memory). Data masking may be used by the host to byte align write data within the memory or to enable
merging of multiple non-word aligned writes in a single burst write. During write transactions, data is center aligned with the clock.
Read and write transactions are burst oriented, transferring the next sequential word during each clock cycle. Each individual read
or write transaction can use either a wrapped or linear burst sequence. During wrapped transactions, accesses start at a selected
location and continue to the end of a configured word group aligned boundary, then wrap to the beginning location in the group, then
continue back to the starting location. Wrapped bursts are generally used for critical word first instruction or data cache line fill read
accesses. During linear transactions, accesses start at a selected location and continue in a sequential manner until the transaction
is terminated when CS# returns High. Linear transactions are generally used for large contiguous data transfers such as graphic
image moves. Since each transaction command selects the type of burst sequence for that access, wrapped and linear burst
transactions can be dynamically intermixed as needed.
For additional information on HyperBus interface operation, please refer to the HyperBus specification.
Document Number: 001-97964 Rev. *E
Page 3 of 29
CYPRESS [ CYPRESS ]
