ADVANCE
S27KL0641, S27KS0641
Each register is written with a separate single word write transaction. Register write transactions have zero latency, the single word
of data immediately follows the Command-Address. RWDS is not driven by the host during the write because RWDS is always
driven by the memory during the CA cycles to indicate whether a memory array refresh is in progress. Because a register space
write goes directly to a register, rather than the memory array, there is no initial write latency, related to an array refresh that may be
in progress. In a register write, RWDS is also not used as a data mask because both bytes of a register are always written and never
masked.
Reserved register fields must be written with their default value. Writing reserved fields with other than default values may produce
undefined results.
Reading of a register is accomplished with a single 16 bit read transaction with CA[46]=1 to select register space. If more than one
word is read, the same register value is repeated in each word read. The CA[45] burst type is “don’t care” because only a single
register value is read. The contents of the register is returned in the same manner as reading array data, with one or two latency
counts, based on the state of RWDS during the Command-Address period. The latency count is defined in the Configuration
Register 0 Read Latency field (CR0[7:4]).
5.2.1
Configuration Register 0
Configuration Register 0 (CR0) is used to define the power mode and access protocol operating conditions for the HyperRAM
device. Configurable characteristics include:
Wrapped Burst Length (16, 32, 64, or 128-byte aligned and length data group)
Wrapped Burst Type
– Legacy wrap (sequential access with wrap around within a selected length and aligned group)
– Hybrid wrap (Legacy wrap once then linear burst at start of the next sequential group)
Initial Latency
Variable Latency
– Whether an array read or write transaction will use fixed or variable latency. If fixed latency is selected the memory will always
indicate a refresh latency and delay the read data transfer accordingly. If variable latency is selected, latency for a refresh is
only added when a refresh is required at the same time a new transaction is starting.
Output Drive Strength
Deep Power Down Mode
Table 5.4 Configuration Register 0 Bit Assignments
CR0 Bit
Function
Settings (Binary)
1 - Normal operation (default)
0 - Writing 0 to CR[15] causes the device to enter Deep Power Down
15
Deep Power Down Enable
000 - 34 ohms (default)
001 - 115 ohms
010 - 67 ohms
011 - 46 ohms
100 - 34 ohms
101 - 27 ohms
110 - 22 ohms
111 - 19 ohms
14-12
11-8
Drive Strength
Reserved
1 - Reserved (default)
Reserved for Future Use. When writing this register, these bits should be set
to 1 for future compatibility.
Document Number: 001-97964 Rev. *E
Page 9 of 29
CYPRESS [ CYPRESS ]
