Package Pin Description: continued
PACKAGE PIN #
PIN SYMBOL
FUNCTION
14
COFF2
Off-Time Capacitor Pin. A capacitor from this pin to LGnd sets the off
time for the non-synchronous regulator (VI/O).
13
COMP2
VI/O section error amp output. PWM comparator inverting input. A
capacitor to LGnd provides error amp compensation.
VI/O section current limit comparator inverting input.
VI/O section error amp inverting feedback input.
12
11
10
VOUT2
VFB2
VFFB2
VI/O PWM comparator fast feedback non-inverting input. VI/O sec-
tion current limit comparator non-inverting input.
9
7
LGnd
VFB1
Logic ground.
VCORE section error amp inverting input, PWRGD and OVP compara-
tor input.
6
5
VOUT1
COMP1
VCORE section current limit comparator inverting input.
VCORE section error amp output. VCORE section PWM comparator
inverting input. A capacitor to LGnd provides error amp compensa-
tion.
4
8
COFF1
VFFB1
Off-Time Capacitor Pin. A capacitor from this pin to LGnd sets the off
time for the synchronous regulator (VCORE).
VCORE section PWM comparator fast feedback non-inverting input.
VCORE section current limit comparator non-inverting input.
Block Diagram
VFFB1
COMP1
COFF1
VCC1
VCC2
PWM
COMP1
UVLO
-
+
+
1.06V
EA1
VFB1
-
-
GATE(H)
Off Time1
One Shot
+
+
Discharge
Comparator
Current
Limit1
PGnd
-
Non-overlap
Logic
Q
86mV
R
VOUT1
VID0
+
-
+
-
Fault
+
-
Latch1
0.25V
GATE(L)
COFF2
S
VID1
VID2
VID3
VID4
DAC
PGnd
PGnd
PWM
COMP2
-
GATE
+
-
+
Off Time2
One Shot
1.10V
+
-
VFFB2
VFB2
-
+
-
+
EA2
-
Discharge
Comparator
+
-
0.25V
Q
+
86mV
-
+
-
VOUT2
R
+
-
PWRGD
OVP
1.23V
Fault
Latch2
Current
Limit2
+
VCC1
S
COMP2
LGnd
PGnd
3
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
