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CS5132GDW24 参数 Datasheet PDF下载

CS5132GDW24图片预览
型号: CS5132GDW24
PDF下载: 下载PDF文件 查看货源
内容描述: 双CPU输出降压控制器 [Dual Output CPU Buck Controller]
分类和应用: 控制器
文件页数/大小: 19 页 / 242 K
品牌: CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
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Absolute Maximum Ratings  
VMAX  
VMIN  
-0.3V  
-0.3V  
ISOURCE  
N/A  
ISINK  
Pin Symbol  
VCC1  
Pin Name  
IC Logic and Low Side Driver Power Input  
IC High Side Drivers Power Input  
16V  
16V  
1.5A Peak  
200mA DC  
3A Peak  
400mA DC  
5mA  
VCC2  
N/A  
COMP1, COMP2  
Compensation Pins for the VCORE  
and VI/O error amplifiers.  
6V  
-0.3V  
1mA  
1mA  
1mA  
V
FB1, VOUT1, VID0-4, VCORE Voltage Feedback Input Pin,  
VOUT2, VFB2, VFFB1  
,
VCORE Output Voltage Sense Pin,  
VFFB2  
Voltage ID DAC Input Pins, VI/O Output Voltage  
Sense Pin, VI/O Voltage Feedback Input Pin,  
6V  
-0.3V  
1mA  
V
CORE PWM comparator Fast Feedback Pin, VI/O  
PWM comparator Fast Feedback Pin.  
COFF1, COFF2  
Off-Time Pins for the VCORE and VI/O regulators  
6V  
-0.3V  
-0.3V  
50mA  
GATE(H), GATE  
High-Side FET Drivers for the VCORE  
and VI/O regulators.  
16V  
1.5A Peak  
200mA DC  
1.5A Peak  
200mA DC  
GATE(L)  
PWRGD  
OVP  
Low-Side FET Driver  
Power-Good Output  
Overvoltage Protection  
Power Ground  
16V  
6V  
-0.3V  
-0.3V  
-0.3V  
0V  
1.5A Peak  
200mA DC  
1mA  
1.5A Peak  
200mA DC  
30mA  
15V  
0V  
30mA  
1mA  
N/A  
PGnd  
3A Peak  
400mA DC  
LGnd  
Logic Ground  
0V  
0V  
40mA  
N/A  
Operating Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 125¡C  
Lead Temperature Soldering:  
Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 sec max. above 183ûC, 230ûC Peak  
Storage Temperature Range, TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150ûC  
ESD Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2  
Package Pin Description  
PACKAGE PIN #  
PIN SYMBOL  
FUNCTION  
23,24,1,2,3  
VIDO Ð VID4  
Voltage ID DAC inputs. These pins are internally pulled up to 5.65V if  
left open. VID4 selects the DAC range. When VID4 is high (logic one),  
the Error Amp reference range is 2.125V to 3.525V with 100mV incre-  
ments. When VID4 is low (logic zero), the Error amp reference voltage  
is 1.325V to 2.075V with 50mV increments.  
20  
VCC1  
Input power supply pin for the internal circuitry, and low side gate  
driver. Decouple with filter capacitor to PGnd.  
17  
18  
19  
16  
GATE(H)  
PGnd  
GATE(L)  
VCC2  
High side switch FET driver pin for VCORE section.  
Power ground for VCORE and VI/O section.  
Low side synchronous FET driver pin.  
Input power supply pin for on-board high side gate drivers. Decouple  
with filter capacitor to PGnd.  
15  
21  
GATE  
OVP  
High side switch FET driver pin for VI/O section.  
Overvoltage protection pin. Goes high when overvoltage condition is  
detected on VFB1  
.
22  
PWRGD  
Power-Good Output. Open collector output drives low when VFB1 is  
out of regulation.  
2