Application Information
Line and load regulation are drastically improved because
Theory Of Operation
there are two independent voltage loops. A voltage mode
controller relies on a change in the error signal to compen-
sate for a deviation in either line or load voltage. This
change in the error signal causes the output voltage to
change corresponding to the gain of the error amplifier,
which is normally specified as line and load regulation.
TM
V2 Control Method
The V2TM method of control uses a ramp signal that is gen-
erated by the ESR of the output capacitors. This ramp is
proportional to the AC current through the main inductor
and is offset by the value of the DC output voltage. This
control scheme inherently compensates for variation in
either line or load conditions, since the ramp signal is gen-
erated from the output voltage itself. This control scheme
differs from traditional techniques such as voltage mode,
which generates an artificial ramp, and current mode,
which generates a ramp from inductor current.
A current mode controller maintains fixed error signal
under deviation in the line voltage, since the slope of the
ramp signal changes, but still relies on a change in the
error signal for a deviation in load. The V2TM method of
control maintains a fixed error signal for both line and load
variation, since the ramp signal is affected by both line and
load.
PWM
Constant Off-Time
Comparator
+
To minimize transient response, the CS5132 uses a
Constant Off-Time method to control the rate of output
pulses. During normal operation, the Off-Time of the high
side switch is terminated after a fixed period, set by the
COFF capacitor. Every time the VFFB pin exceeds the COMP
pin voltage an Off-Time is initiated. To maintain regula-
tion, the V2TM Control Loop varies switch On-Time. The
PWM comparator monitors the output voltage ramp, and
terminates the switch On-Time.
Constant Off-Time provides a number of advantages.
Switch duty Cycle can be adjusted from 0 to 100% on a
pulse-by pulse basis when responding to transient condi-
tions. Both 0% and 100% Duty Cycle operation can be
maintained for extended periods of time in response to
Load or Line transients.
GATE(H)
C
GATE(L)
Ð
V
Output
FFB
Ramp Signal
Voltage
Feedback
V
FB
Error
Amplifier
Ð
+
COMP
E
Reference
Voltage
Error
Signal
Figure 1: V2TM Control Diagram.
The V2TM control method is illustrated in Figure 1. The out-
put voltage is used to generate both the error signal and
the ramp signal. Since the ramp signal is simply the output
voltage, it is affected by any change in the output regard-
less of the origin of that change. The ramp signal also con-
tains the DC portion of the output voltage, which allows
the control circuit to drive the main switch to 0% or 100%
duty cycle as required.
Programmable Output
The CS5132 is designed to provide two methods for pro-
gramming the output voltage of the power supply. A five
bit on board digital to analog converter (DAC) is used to
program the output voltage within two different ranges.
The first range is 2.125V to 3.525V in 100mV steps, the sec-
ond is 1.325V to 2.075V in 50mV steps, depending on the
digital input code. If all five bits are left open, the CS5132
enters adjust mode. In adjust mode, the designer can
choose any output voltage by using resistor divider feed-
back to the VFB pin, as in traditional controllers. The
CS5132 is specifically designed to meet or exceed IntelÕs
Pentium¨ II specifications.
A change in line voltage changes the current ramp in the
TM
inductor, affecting the ramp signal, which causes the V2
control scheme to compensate the duty cycle. Since the
change in inductor current modifies the ramp signal, as in
current mode control, the V2TM control scheme has the
same advantages in line transient response.
A change in load current will have an affect on the output
voltage, altering the ramp signal. A load step immediately
changes the state of the comparator output, which controls
the main switch. Load transient response is determined
only by the comparator response time and the transition
speed of the main switch. The reaction time to an output
load step has no relation to the crossover frequency of the
error signal loop, as in traditional control methods.
The error signal loop can have a low crossover frequency,
since transient response is handled by the ramp signal
loop. The main purpose of this ÔslowÕ feedback loop is to
provide DC accuracy. Noise immunity is significantly
improved, since the error amplifier bandwidth can be
rolled off at a low frequency. Enhanced noise immunity
improves remote sensing of the output voltage, since the
noise associated with long feedback traces can be effective-
ly filtered.
Error Amplifier
An inherent benefit of the V2TM control topology is that
there is no large bandwidth requirement on the error
amplifier design. The reaction time to an output load step
has no relation to the crossover frequency, since transient
response is handled by the ramp signal loop. The main
purpose of thisÓslowÓfeedback loop is to provide DC accu-
racy. Noise immunity is significantly improved, since the
error amplifier bandwidth can be rolled off at a low fre-
quency. Enhanced noise immunity improves remote sens-
ing of the output voltage, since the noise associated with
long feedback traces can be effectively filtered. The COMP
pin is the output of the error amplifier and a capacitor to
LGnd compensates the error amplifier loop. Additionally,
through the built-in offset on the PWM Comparator non-
inverting input, the COMP pin provides the hiccup timing
for the Over-Current Protection, the soft start function that
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