Block Diagram
COMP1
V
FFB1
+
PWM
V
FB1
-
Comparator
Error
Amplifier
-
Channel 2
Gate Driver
GATE1
+
1.275V
V
REF
Bandgap
Voltage
Reference
VIN
Reference
Undervoltage
Lockout
V
Undervoltage
Lockout
IN
LGND
PGND
SYNC
Oscillator
R
T
Channel 2
Gate Driver
+
C
T
GATE2
1.275V
Error
-
Amplifier
PWM
V
-
Comparator
FB2
+
COMP2
V
FFB2
ENABLE
Theory of Operation
2ª
The V
The CS5127 is a dual power supply controller that utilizes
control method is illustrated in Figure 1. Both
2ª
2ª
buck
the V control method. Two nonsynchronous V
the ramp signal and the error signal are generated by the
output voltage. Since the ramp voltage is defined as the
output voltage, the ramp signal is affected by any change
in the output, regardless of the origin of that change. The
ramp signal also contains the DC portion of the output
voltage, allowing the control circuit to drive the output
switch from 0% to about 90% duty cycle.
regulators can be built using a single controller IC. This IC
is a perfect choice for efficiently and economically provid-
ing core power and I/O power for the latest
high-performance CPUs. Both switching regulators
employ a fixed frequency architecture driven from a
common oscillator circuit.
Changes in line voltage will change the current ramp in
2ª
V
Control Method
the inductor, affecting the ramp signal and causing the
2ª
V
control loop to adjust the duty cycle. Since a change
2ª
2ª
The V
method of control uses a ramp signal generated
in inductor current changes the ramp signal, the V
method has the characteristics and advantages of current
mode control for line transient response.
by the ESR of the output capacitors. This ramp is propor-
tional to the AC current in the inductor and is offset by the
2ª
DC output voltage. V
inherently compensates for varia-
Changes in load current will affect the output voltage and
tion in both line and load conditions since the ramp signal
is generated from the output voltage. This differs from tra-
ditional methods such as voltage mode control, where an
artificial ramp signal must be generated, and current mode
control, where a ramp is generated from inductor current.
thus will also change the ramp signal. A load step will
immediately change the state of the comparator output
that controls the output switch. In this case, load transient
response time is limited by the comparator response time
and the transition speed of the switch. Notice that the reac-
2ª
tion time of the V
loop to a load transient is not
dependent on the crossover frequency of the error signal
loop. Traditional voltage mode and current mode methods
are dependent on the compensation of the error signal
loop.
+
GATE
PWM
Comparator
-
2ª
The V
error signal loop can have a low crossover fre-
V
FFB
Ramp Signal
quency, since transient response is handled by the ramp
signal loop. The ÒslowÓ error signal loop provides DC
accuracy. Low frequency roll-off of the error amplifier
bandwidth will significantly improve noise immunity.
This also improves remote sensing of the output voltage,
since switching noise picked up in long feedback traces
can be effectively filtered.
V
FB
Error Signal
-
Error
Amplifier
COMP
Reference
Voltage
+
2ª
2ª
V
line and load regulation are dramatically improved
Figure 1: V
control diagram.
because there are two separate control loops. A voltage
5
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
