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24LLC08A 参数 Datasheet PDF下载

24LLC08A图片预览
型号: 24LLC08A
PDF下载: 下载PDF文件 查看货源
内容描述: [EEPROM, 1KX8, Serial, CMOS, PDSO8,]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管内存集成电路
文件页数/大小: 19 页 / 377 K
品牌: CERAMATE [ CERAMATE TECHNICAL ]
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24LLC08  
8K-Bit Serial EEPROM  
I2C-BUS PROTOCOLS  
Here are several rules for I2C-bus transfers:  
— A new data transfer can be initiated only when the bus is currently not busy.  
— MSB is always transferred first in transmitting data.  
— During a data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is High.  
The I2C-bus interface supports the following communication protocols:  
·
·
Bus not busy: The SDA and the SCL lines remain High level when the bus is not active.  
Start condition: Start condition is initiated by a High-to-Low transition of the SDA line while SCL remains High  
level. All bus commands must be preceded by a start condition.  
·
Stop condition: A stop condition is initiated by a Low-to-High transition of the SDA line while SCL remains  
High level. All bus operations must be completed by a stop condition (see Figure 3-7).  
SCL  
SDA  
Start  
Data or  
Data  
Stop  
Condition  
ACK Valid Change  
Condition  
Figure 3-7. Data Transmission Sequence  
·
·
Data valid: Following a start condition, the data becomes valid if the data line remains stable for the duration  
of the High period of SCL. New data must be put onto the bus while SCL is Low. Bus timing is one clock  
pulse per data bit. The number of data bytes to be transferred is determined by the master device. The total  
number of bytes that can be transferred in one operation is theoretically unlimited.  
ACK (Acknowledge): An ACK signal indicates that a data transfer is completed successfully. The transmitter  
(the master or the slave) releases the bus after transmitting eight bits. During the 9th clock, which the master  
generates, the receiver pulls the SDA line low to acknowledge that it successfully received the eight bits of  
data (see Figure 3-8). But the slave does not send an ACK if an internal write cycle is still in progress.  
In data read operations, the slave releases the SDA line after transmitting 8 bits of data and then monitors  
the line for an ACK signal during the 9th clock period. If an ACK is detected, the slave will continue to  
transmit data. If an ACK is not detected, the slave terminates data transmission and waits for a stop condition  
to be issued by the master before returning to its stand-by mode.  
* All specs and applications shown above subject to change without prior notice.  
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN  
Tel:886-3-3214525  
Email: server@ceramate.com.tw  
Http: www.ceramate.com.tw  
Rev 1.0 Nov. 18, 2002  
Page 6 of 19  
Fax:886-3-3521052  
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