24LLC08
8K-Bit Serial EEPROM
BYTE WRITE OPERATION
In a complete byte write operation, the master transmits the slave address, word address, and one data byte to
the 24LLC08 (see Figure 3-9).
Start Slave Address
Word Address
Data
Stop
A
C
K
A
C
K
A
C
K
Figure 3-9. Byte Write Operation
Following the Start condition, the master sends the device identifier (4 bits), the device address (3 bits), and an
R/W bit set to “0” onto the bus. Then the addressed 24LLC08 generates an ACK and waits for the next byte.
The next byte to be transmitted by the master is the word address. This 8-bit address is written into the word
address pointer of the 24LLC08.
When the 24LLC08 receives the word address, it responds by issuing an ACK and then waits for the next 8-bit
data. When it receives the data byte, the 24LLC08 again responds with an ACK. The master terminates the
transfer by generating a Stop condition, at which time the 24LLC08 begins the intermal write cycle.
While the internal write cycle is in progress, all 24LLC08 inputs are disabled and the 24LLC08 does not respond
to additional requests from the master.
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Tel:886-3-3214525
Email: server@ceramate.com.tw
Http: www.ceramate.com.tw
Rev 1.0 Nov. 18, 2002
Page 8 of 19
Fax:886-3-3521052
CERAMATE [ CERAMATE TECHNICAL ]
