24LLC08
8K-Bit Serial EEPROM
SDA
WP
Start/Stop
Logic
HV Generation
Timing Control
Control Logic
EEPROM
Cell Array
SCL
Slave Address
Comparator
Word Address
Pointer
Row
decoder
1024 x 8 bits
A0
A1
A2
Column Decoder
Data Register
DOUT and ACK
Figure 3-1. 24LLC08 Block Diagram
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
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Rev 1.0 Nov. 18, 2002
Page 2 of 19
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