24LLC08  
					8K-Bit Serial EEPROM  
					SDA  
					WP  
					Start/Stop  
					Logic  
					HV Generation  
					Timing Control  
					Control Logic  
					EEPROM  
					Cell Array  
					SCL  
					Slave Address  
					Comparator  
					Word Address  
					Pointer  
					Row  
					decoder  
					1024 x 8 bits  
					A0  
					A1  
					A2  
					Column Decoder  
					Data Register  
					DOUT and ACK  
					Figure 3-1. 24LLC08 Block Diagram  
					* All specs and applications shown above subject to change without prior notice.  
					1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN  
					Tel:886-3-3214525  
					Email: server@ceramate.com.tw  
					Http: www.ceramate.com.tw  
					Rev 1.0 Nov. 18, 2002  
					Page 2 of 19  
					Fax:886-3-3521052