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NES1720P-140 参数 Datasheet PDF下载

NES1720P-140图片预览
型号: NES1720P-140
PDF下载: 下载PDF文件 查看货源
内容描述: [RF Power Field-Effect Transistor, 2-Element, L Band, Gallium Arsenide, N-Channel, Metal Semiconductor FET, T-92, 4 PIN]
分类和应用: 局域网放大器晶体管
文件页数/大小: 4 页 / 38 K
品牌: CEL [ CALIFORNIA EASTERN LABS ]
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PRELIMINARY DATA SHEET
140 W L-BAND TWIN POWER GaAs MESFET
NES1720P-140
FEATURES
HIGH OUTPUT POWER:
140 W TYP
HIGH LINEAR GAIN:
11 dB TYP
HIGH EFFICIENCY:
42% TYP
USABLE IN BALANCED OR PUSH-PULL
CONFIGURATION.
OUTLINE DIMENSIONS
(Units in mm)
PACKAGE OUTLINE T-92
9.7
±
0.3
R1.2
±
0.3
2.4
±
0.3
45°
3.0
±
0.4
45°
G1
G2
DESCRIPTION
The NES1720P-140 is a "twin" transistor device consisting of
two pairs of GaAs MESFET chips which may be combined
externally in either balanced or push-pull configurations. It is
designed for PCS base stations and repeaters for mobile and
fixed wireless (WLL) systems, and with modification of the
external matching circuit, can be used for 1.7-2.0 GHz applica-
tions. It is capable of delivering 140 W of output power (CW)
with high gain, high efficiency and excellent linearity. The
device employs 0.9
µm
Tungsten Silicide gates, via holes,
plated heat sink, and silicon dioxide and nitride passivation for
superior performance, thermal characteristics, and reliability.
Reliability and performance uniformity are assured by NEC's
stringent quality control procedures.
8.0
±
0.3
S
S
17.4
±
0.3
D1
4.0
±
0.3
D2
3.0
±
0.4
31.6
±
0.3
35.2
±
0.3
24.6
±
0.3
4.75 MAX
2.4
±
0.2
1.8
±
0.2
G1, G2 : Gate
D1, D2 : Drain
S : Source
= 40°C)
NES1720P-140
T-92
UNITS
dBm
dB
%
A
A
V
K/W
-4.0
MIN
50.5
10
TYP
51.5
11
42
24
76
-2.6
0.4
0.55
MAX
TEST CONDITIONS
V
DS
= 12 V
f = 1.93 & 1.99 GHz
I
DSQ
= 6.0 A Total (RF off)
P
IN
= 43.0 dBm
R
G1
= 5
(Each Side)
V
DS
= 2.5 V; V
GS
= 0 V
V
DS
= 2.5 V; I
DS
= 330 mA
T
F
= 25°C; V
DS
= 12 V;
I
DS
= 8.0 A
ELECTRICAL AND THERMAL CHARACTERISTICS
(T
F
PART NUMBER
PACKAGE OUTLINE
SYMBOLS
CHARACTERISTICS
Output Power
Linear Gain
Power-Added Efficiency
Drain Current
Saturated Drain Current
Pinch-off Voltage
Thermal Resistance Channel-to-Flange
Functional
Characteristics
P
OUT
G
L
η
ADD
I
D
Electrical DC
Characteristics
I
DSS
V
P
R
TH
Note:
1. R
G
is the series resistance between the gate supply and the FET gate.
2. To calculate R
TH
versus T
F
and T
CH
(or P
DISS
), see AN1032 "Microwave Power GaAs Device Thermal Resistance Basics" application note.
For the initial values use: R
TH1
= 0.55 K/W, T
F1
= 25˚C, T
CH1
= 77.8˚C and for R
F
use R
F
= 0.18 K/W.
California Eastern Laboratories