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SBAS324 − JUNE 2004
SWITCHING CHARACTERISTICS
T
= −40°C, T = +85°C. Typical values are at T = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V,
MIN
MAX A
LVDD = 3.3V, −1dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
ADS5272
MIN
TYP
MAX
PARAMETER
CONDITIONS
UNITS
SWITCHING SPECIFICATIONS
t
25
50
ns
ns
SAMPLE
t (A) Aperture Delay
2.5
1
D
Aperture Jitter (uncertainty)
t (pipeline) Latency
ps
6.5
5
cycles
ns
D
t
Propagation Delay
PROP
SERIAL INTERFACE TIMING
Data is shifted in MSB first.
Outputs change on
next rising clock edge
after CS goes high.
ADCLK
Start Sequence
CS
t1
Data latched on
each rising edge of SCLK.
t2
SCLK
t3
SDATA
MSB
D6
D5
D4
D3
D2
D1
D0
t4
t5
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
ns
t
1
t
2
t
3
t
4
t
5
Serial CLK Period
50
Serial CLK High Time
Serial CLK Low Time
25
25
5
ns
ns
Minimum Data Setup Time
Minimum Data Hold Time
ns
5
ns
5
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