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SBAS324 − JUNE 2004
ELECTRICAL CHARACTERISTICS
T
= −40°C, and T
= +85°C. Typical values are at T = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V,
MIN
MAX A
LVDD = 3.3V, −1dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
ADS5272
MIN
TYP
MAX
PARAMETER
TEST CONDITIONS
UNITS
DC ACCURACY
No Missing Codes
Assured
0.5
0.6
0.2
14
DNL Differential Nonlinearity
INL Integral Nonlinearity
f
f
= 5MHz
= 5MHz
−0.9
−2.0
TBD
0.9
2.0
LSB
LSB
IN
IN
(1)
Offset Error
TBD
%FS
Offset Temperature Coefficient
ppm/°C
%FS
(2)
Fixed Attenuation in Channel
1
(3)
Variable Attenuation in Channel
0.2
1.0
44
%FS
(4)
Gain Error
REF − REF
TBD
TBD
%FS
T
B
(5)
Gain Temperature Coefficient
ppm/°C
POWER SUPPLY
I
Total Supply Current
V
V
= FS, F = 5MHz
302
TBD
TBD
996
90
mA
mA
mA
mW
mW
CC
IN
IN
I(AVDD) Analog Supply Current
= FS, F = 5MHz
IN
IN
I(LVDD) Digital Output Driver Supply Current
Power Dissipation
V
IN
= FS, F = 5MHz, LVDS Into 100Ω Load
IN
TBD
Power Down
Clock Running
REFERENCE VOLTAGES
VREF Reference Top (internal)
1.95
0.95
1.45
2.0
1.0
1.5
2
2.05
1.05
1.55
V
V
T
VREF
Reference Bottom (internal)
B
V
CM
Common-Mode Voltage
(6)
V
V
Output Current
50mV Change in Voltage
mA
V
CM
VREF
Reference Top (external)
1.875
T
VREF
Reference Bottom (external)
External Reference Input Current
1.125
V
B
(7)
2.0
7.0
mA
ANALOG INPUT
Differential Input Capacitance
pF
V
Analog Input Common-Mode Range
Differential Input Voltage Range
V
0.05
CM
1.5
2.02
V
PP
Differential Input Signal at 4V
Recovery to Within 1% of Code
PP
Voltage Overload Recovery Time
Input Bandwidth
4.0
CLK Cycles
MHz
−3dBFS
300
DIGITAL DATA OUTPUTS
Data Bit Rate
SERIAL INTERFACE
SCLK Serial Clock Input Frequency
340
780
MBPS
20
0.6
MHz
V
V
LOW Input Low Voltage
HIGH Input High Voltage
Input Current
0
IN
V
IN
2.1
VDD
V
10
µA
pF
Input Pin Capacitance
5.0
(1)
(2)
Offset error is the deviation of the average code from mid-code for a zero input. Offset error is expressed in terms of % of full-scale.
Fixed attenuation in the channel arises due to a fixed attenuation of about 1% in the sample-and-hold amplifier. When the differential voltage at the analog input pins are
changed from −V to +V , the swing of the output code is expected to deviate from the full-scale code (4096LSB) by the extent of this fixed attenuation [V is defined
REF
REF
REF
as (REF − REF )].
T
B
(3)
(4)
(5)
Variable attenuation in the channel refers to the attenuation of the signal in the channel over and above the fixed attenuation.
The reference voltages are trimmed at production so that (VREF − VREF ) is within 25mV of the ideal value of 1V. It does not include fixed attenuation.
The gain temperature coefficient refers to the temperature coefficient of the attenuation in the channel. It does not account for the variation of the reference voltages with
temperature.
T
B
(6)
(7)
V
the V
provides the common-mode current for the inputs of all eight channels when the inputs are AC-coupled. The V
output current specified is the additional drive of
CM
CM
buffer if loaded externally.
CM
Average current drawn from the reference pins in the external reference mode.
3
BB [ BURR-BROWN CORPORATION ]
