ADS5272
SBAS324 − JUNE 2004
8-Channel, 12-Bit, 65MSPS ADC
with Serial LVDS Interface
FEATURES
D
D
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D
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Maximum Sample Rate: 65MSPS
12-Bit Resolution
No Missing Codes
Power Dissipation: 996mW
CMOS Technology
Simultaneous Sample-and-Hold
70.5dB SNR at 10MHz IF
Internal and External References
3.3V Digital/Analog Supply
Serialized LVDS Outputs
Integrated Frame and Synch Patterns
MSB and LSB First Modes
Option to Double LVDS Clock Output Currents
Pin- and Format-Compatible Family
TQFP-80 PowerPAD Package
or LSB first. The bit coinciding with the rising edge of the 1x
clock output is the first bit of the word. Data is to be latched by
the receiver on both the rising and falling edges of the 6x clock.
The ADS5272 provides internal references, or can optionally
be driven with external references. Best performance can be
achieved through the internal reference mode.
The device is available in a TQFP-80 PowerPAD package and
is specified over a −40°C to +85°C operating range.
6X ADCLK
LCLK
P
PLL
ADCLK
1X ADCLK
ADCLK
P
ADCLK
N
IN1
P
IN1
N
IN2
P
IN2
N
IN3
P
IN3
N
IN4
P
IN4
N
IN5
P
IN5
N
IN6
P
IN6
N
IN7
P
IN7
N
IN8
P
IN8
N
S/H
12−Bit
ADC
Serializer
OUT1
P
OUT1
N
OUT2
P
OUT2
N
OUT3
P
OUT3
N
OUT4
P
OUT4
N
OUT5
P
OUT5
N
OUT6
P
OUT6
N
OUT7
P
OUT7
N
OUT8
P
OUT8
N
S/H
12−Bit
ADC
Serializer
APPLICATIONS
Portable Ultrasound Systems
Tape Drives
Test Equipment
Optical Networking
S/H
12−Bit
ADC
Serializer
S/H
12−Bit
ADC
Serializer
DESCRIPTION
The ADS5272 is a high-performance, 65MSPS, 8-channel,
parallel analog-to-digital converter (ADC). Internal references
are provided, simplifying system design requirements. Low
power consumption allows for the highest of system
integration densities. Serial LVDS (low-voltage differential
signaling) outputs reduce the number of interface lines and
package size.
An integrated phase lock loop multiplies the incoming ADC
sampling clock by a factor of 12. This 12x clock is used in the
process of serializing the data output from each channel. The
12x clock is also used to generate a 1x and a 6x clock, both
of which are transmitted as LVDS clock outputs. The 6x clock
is denoted by the differential pair LCLKP and LCLKN, while the
1x clock is denoted by ADCLKP and ADCLKN. The word
output of each ADC channel can be transmitted either as MSB
S/H
12−Bit
ADC
Serializer
S/H
12−Bit
ADC
Serializer
S/H
12−Bit
ADC
Serializer
S/H
12−Bit
ADC
Serializer
Reference
Registers
Control
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the formative or design
phase of development. Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or discontinue these
products without notice.
Copyright
2004, Texas Instruments Incorporated
www.ti.com
SDATA
RESET
CS
SCLK
REF
T
V
CM
REF
B
INT/EXT
PD
PRODUCT PREVIEW
LCLK
N
BURR-BROWN [ BURR-BROWN CORPORATION ]
