ꢠꢃ ꢡꢢ ꢣ ꢤ ꢣ
www.ti.com
SBAS324 − JUNE 2004
AC CHARACTERISTICS
T
= −40°C, T
= +85°C. Typical values are at T = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V,
MIN
MAX A
−1dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
ADS5272
TYP
PARAMETER
DYNAMIC CHARACTERISTICS
CONDITIONS
MIN
MAX
UNITS
f
f
= 1MHz
= 5MHz
= 10MHz
= 20MHz
= 1MHz
= 5MHz
= 10MHz
= 20MHz
= 1MHz
= 5MHz
= 10MHz
= 20MHz
= 1MHz
= 5MHz
= 10MHz
= 20MHz
= 1MHz
= 5MHz
= 10MHz
= 20MHz
87
85
dBc
dBc
IN
IN
TBD
SFDR Spurious-Free Dynamic Range
f
f
85
dBc
IN
83
dBc
IN
f
f
90
dBc
IN
IN
TBD
TBD
TBD
TBD
90
dBc
HD
2nd-Order Harmonic Distortion
3rd-Order Harmonic Distortion
2
3
f
f
89
dBc
IN
IN
86
dBc
f
87
dBc
IN
IN
f
85
dBc
HD
f
f
85
dBc
IN
IN
83
dBc
f
70.5
70.5
70.5
70.5
70
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
IN
IN
f
SNR Signal-to-Noise Ratio
f
f
IN
IN
f
IN
IN
f
70
SINAD Signal-to-Noise and Distortion
f
f
70
IN
IN
70
f
= 9.5MHz at −7dBFS
1
IMD Two-Tone Intermodulation Distortion
ENOB Effective Number of Bits
−85
dBFS
Bits
f
= 10.2MHz at −7dBFS
2
f
= 5MHz
11.3
IN
Signal Applied to 7 Channels;
Measurement Taken on the Channel with
No Input Signal
Crosstalk
−90
dBc
LVDS DIGITAL DATA AND CLOCK OUTPUTS
Test conditions at I = 3.5mA, R
= 100Ω, and C
= 9pF. I refers to the current setting for the LVDS buffer. R
is the differential load resistance
O
LOAD
LOAD
O
LOAD
between the differential LVDS pair. C
is the effective single-ended load capacitance between the differential LVDS pins and ground. C
includes the
LOAD
LOAD
receiver input parasitics as well as the routing parasitics. Measurements are done with a transmission line of 100Ω differential impedance between the device and
the load. All LVDS specifications are functionally tested, but not parametrically tested.
PARAMETER
(1)
CONDITIONS
MIN
TYP
MAX
UNITS
DC SPECIFICATIONS
Output Voltage High, OUT or OUT
V
R
R
= 100Ω 1%; See LVDS Timing Diagram, Page 7
1375
1025
350
1200
4
1500
mV
mV
mV
mV
pF
OH
P
N
LOAD
V
Output Voltage Low, OUT or OUT
R
= 100Ω 1%
= 100Ω 1%
900
300
OL
P
N
LOAD
LOAD
V
V
Output Differential Voltage, OUT − OUT
Output Offset Voltage
R
400
OD
P
N
(2)
= 100Ω 1%; See LVDS Timing Diagram, Page 7
1100
1300
OS
LOAD
(3)
C
Output Capacitance
V
= 1.5V
O
CM
∆V
∆V
Change in V Between 0 and 1
Change Between 0 and 1
R
R
= 100Ω 1%
= 100Ω 1%
25
25
40
12
mV
mV
mA
mA
OD
OD
LOAD
OS
LOAD
ISOUT Output Short-Circuit Current
ISOUT Output Current
Drivers Shorted to Ground
Drivers Shorted Together
NP
DRIVER AC SPECIFICATIONS
Clock Clock Signal Duty Cycle
Minimum Data Setup TIme
6 × ADCLK
45
50
55
%
ps
ps
(4, 5)
650
650
400
250
200
150
(4, 5)
Minimum Data Hold Time
Rise Time or V Fall Time
t
/t
V
I
I
I
= 2.5mA
= 3.5mA
= 4.5mA
RISE FALL
OD
OD
O
O
O
ps
ps
ps
I
= 6mA
O
(1)
(2)
(3)
(4)
(5)
The DC specifications refer to the condition where the LVDS outputs are not switching, but are permanently at a valid logic level 0 or 1.
refers to the common-mode of OUT and OUT
V
.
N
OS
P
Output capacitance inside the device, from either OUT or OUT to ground.
P
N
Refer to the LVDS application note (SBAA118) for a description of data setup and hold times.
Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume that the data and clock
paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as reduced timing margins.
4
BB [ BURR-BROWN CORPORATION ]
