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ADS1245IDGST 参数 Datasheet PDF下载

ADS1245IDGST图片预览
型号: ADS1245IDGST
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗,24位模拟数字转换器 [Low-Power, 24-Bit Analog-to-Digital Converter]
分类和应用: 转换器
文件页数/大小: 19 页 / 252 K
品牌: BB [ BURR-BROWN CORPORATION ]
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www.ti.com  
ꢉ ꢃꢠ ꢡꢢ ꢣꢤ  
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003  
ELECTRICAL CHARACTERISTICS  
All specifications at T = −40°C to +85°C, AVDD = +5V, DVDD = +3V, f  
= 2.4576MHz, and V  
= +1.25V, unless otherwise noted.  
A
CLK  
REF  
PARAMETER  
Analog Input  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Full-scale input voltage range  
Absolute input range  
Differential input impedance  
System Performance  
Resolution  
AINP − AINN  
AINP, AINN with respect to GND  
= 2.4576MHz  
2V  
REF  
V
V
GND + 0.1  
24  
AVDD − 1.25  
f
3
GΩ  
CLK  
No missing codes  
= 2.4576MHz  
Bits  
(1)  
Data rate  
f
15  
0.0006  
1
SPS  
CLK  
Differential input signal, end point fit  
(2)  
Integral nonlinearity (INL)  
Offset error  
0.0015  
14  
%FSR  
ppm of FSR  
(3)  
Offset error drift  
(4)  
Gain error  
0.01  
0.005  
0.5  
ppm of FSR/°C  
0.1  
%
ppm/°C  
dB  
(3)  
Gain error drift  
At DC  
90  
100  
100  
60  
100  
(5)  
f
f
f
f
= 50 1Hz, f  
= 2.4576MHz  
= 2.4576MHz  
dB  
Common-mode rejection  
CM  
CM  
SIG  
SIG  
CLK  
= 60 1Hz, f  
(6)  
dB  
CLK  
= 50 1Hz, f  
= 2.4576MHz  
CLK  
= 2.4576MHz  
dB  
Normal-mode rejection  
Input referred noise  
= 60 1Hz, f  
70  
dB  
CLK  
ppm of FSR,  
RMS  
2
Analog power-supply rejection  
Digital power-supply rejection  
Voltage Reference Input  
At DC, AVDD = 5%  
At DC, AVDD = 5%  
100  
100  
dB  
dB  
(7)  
Reference input voltage (V  
)
V
VREFP − VREFN  
0.5  
1.25  
1
AVDD  
V
V
REF  
REF  
Negative reference input (VREFN)  
Positive reference input (VREFP)  
Voltage reference impedance  
Digital Input/Output  
GND − 0.1  
VREFP − 0.5  
AVDD + 0.1  
VREFN + 0.5  
V
f
= 2.4576MHz  
MΩ  
CLK  
V
V
V
V
(CLK, SCLK)  
(CLK, SCLK)  
0.8 DVDD  
GND  
5.25  
0.2 DVDD  
DVDD  
DVDD + 0.4  
10  
V
V
IH  
IL  
Logic levels  
(DRDY, DOUT)  
(DRDY, DOUT)  
I
I
= 1mA  
= 1mA  
DVDD − 0.4  
GND  
V
OH  
OH  
V
OL  
OL  
Input leakage (CLK, SCLK)  
0 < (CLK, SCLK) < DVDD  
µA  
MHz  
%
CLK frequency (f  
CLK duty cycle  
Power Supply  
AVDD  
)
6
CLK  
30  
70  
2.7  
1.8  
5.25  
3.6  
1
V
V
DVDD  
Sleep mode  
0.1  
152  
158  
0.1  
1.6  
5
µA  
µA  
µA  
µA  
µA  
µA  
mW  
AVDD = 3V  
AVDD current  
DVDD current  
AVDD = 5V  
250  
Sleep mode, CLK stopped  
Sleep mode, 2.4576MHZ CLK running  
DVDD = 3V  
5
10  
Total power dissipation  
AVDD = DVDD = 3V  
0.47  
(1)  
(2)  
(3)  
(4)  
SPS = samples per second.  
FSR = full-scale range = 4V  
REF  
Recalibration can reduce these errors to the level of the noise.  
.
Achieving specified gain error performance requires that calibration be performed with reference voltage input between (GND + 0.1V) and  
(AVDD − 1.25V). See Voltage Reference Inputs section.  
(5)  
(6)  
(7)  
f
f
is the frequency of the common-mode input.  
is the frequency of the input signal.  
CM  
SIG  
It will not be possible to reach the digital output full-scale code when V > 2V  
.
IN REF  
3