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ADS1245IDGST 参数 Datasheet PDF下载

ADS1245IDGST图片预览
型号: ADS1245IDGST
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗,24位模拟数字转换器 [Low-Power, 24-Bit Analog-to-Digital Converter]
分类和应用: 转换器
文件页数/大小: 19 页 / 252 K
品牌: BB [ BURR-BROWN CORPORATION ]
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www.ti.com  
ꢉ ꢃꢠ ꢡꢢ ꢣꢤ  
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003  
To help see the response at lower frequencies, Figure 19  
illustrates the response out to 180Hz. Notice that both  
50Hz and 60Hz signals are rejected. This feature is very  
useful for eliminating power line cycle interference during  
measurements. Figure 20 shows the ADS1245 response  
around these frequencies.  
The ADS1245 data rate and frequency response scale  
directly with CLK frequency. For example, if fCLK  
increases from 2.4576MHz to 4.9152MHz, the data rate  
increases from 15sps to 30sps while the notches in the  
response at 50Hz and 60Hz move out to 100Hz and  
120Hz.  
SETTLING TIME  
0
The ADS1245 has single-cycle settling. That is, the output  
data is fully settled after a single conversion—there is no  
need to wait for additional conversions before retrieving  
the data when there is a change on the analog inputs.  
20  
40  
60  
80  
fCLK = 2.4576MHz  
In order to realize single-cycle settling, synchronize  
changes on the analog inputs to the conversion beginning,  
which is indicated by the falling edge of DRDY/DOUT. For  
example, when using a multiplexer in front of the  
ADS1245, change the multiplexer inputs when  
DRDY/DOUT goes low. Increasing the time between the  
conversion beginning and the change on the analog inputs  
(tDELAY) results in a settling error in the conversion data, as  
shown in Figure 21. The settling error versus delay time is  
shown in Figure 22. If the input change is delayed to the  
point where the settling error is too high, simply ignore the  
first data result and wait for the second conversion, which  
will be fully settled.  
100  
120  
140  
160  
180  
Frequency (Hz)  
Figure 19. Frequency Response to 180Hz  
10.000000  
1.000000  
0.100000  
40  
50  
60  
70  
80  
90  
fCLK = 2.4576MHz  
fCLK = 2.4576MHz  
0.010000  
0.001000  
0.000100  
0.000010  
0.000001  
100  
110  
120  
0
2
4
6
8
10  
12  
14  
16  
45  
50  
55  
Frequency (Hz)  
60  
65  
Delay Time, tDELAY (ms)  
Figure 20. Frequency Response Near  
50Hz and 60Hz  
Figure 21. Settling Error vs Delay Time  
9