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SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
To achieve optimal gain error performance, the reference
input should be maintained within the range GND + 0.1V
to AVDD − 1.25V when performing a self-calibration. A
calibration based on a reference input outside this voltage
range will result in gain errors exceeding specified values,
but not more than 0.5%. Errors due to drift will remain
within specified limits regardless of the calibration
procedure.
subsequent SCLK rising edge. After all 24 bits have been
retrieved, the pin can be forced high with an additional
SCLK. It will then stay high until new data is ready. This is
useful when polling on the status of DRDY/DOUT to
determine when to begin data retrieval.
SERIAL CLOCK INPUT (SCLK)
This digital input shifts serial data out with each rising
edge. As with CLK, this input may be driven with 5V logic
regardless of the DVDD or AVDD voltage. There is
hysteresis built into this input, but care should still be taken
to ensure a clean signal. Glitches or slow-rising signals
can cause unwanted additional shifting. For this reason, it
is best to make sure the rise-and-fall times of SCLK are
less than 50ns.
For best performance, bypass the voltage reference inputs
with a 0.1µF capacitor between VREFP and VREFN.
Place the capacitor as close as possible to the pins.
ESD diodes protect the inputs. To keep these diodes from
turning on, make sure the voltages on the input pins do not
go below GND by more than 100mV, and likewise do not
exceed AVDD by 100mV.
CLOCK INPUT (CLK)
FREQUENCY RESPONSE
This digital input supplies the system clock to the
ADS1245. The recommended CLK frequency is
2.4576MHz. This places the notches of the digital filter at
50Hz and 60Hz and sets the data rate at 15SPS. The CLK
frequency can be increased to speed up the data rate, but
the frequency notches will move proportionally in
frequency. CLK must be left running during normal
operation. It can be turned off during Sleep Mode to save
power, but this is not required. The CLK input can be driven
with 5V logic, regardless of the DVDD or AVDD voltage.
Minimize the overshoot and undershoot on CLK for the
best analog performance. A small resistor in series with
CLK (10Ω to 100Ω) can often help. CLK can be generated
from a number of sources including stand-alone crystal
oscillators and microcontrollers. The MSP430, an ultra low
power microcontroller, is especially well-suited for this
task. Using the MSP430 FLL clock generator available on
the 4xx family, it is easy to produce a 2.4576MHz clock
from a 32.768kHz crystal.
The ADS1245 frequency response for fCLK = 2.4576MHz
is shown in Figure 18. The frequency response repeats at
multiples of 19.2kHz. The overall response is that of a
low-pass filter with a –3dB cutoff frequency of 13.7Hz. As
can be seen, the ADS1245 does a good job attenuating out
to 19kHz. For the best resolution, limit the input bandwidth
to below this value to keep higher frequency noise from
affecting performance. Often, a simple RC filter on the
ADS1245 analog inputs is all that is needed.
0
fCLK = 2.4576MHz
−
−
−
−
20
40
60
80
−
−
−
100
120
140
DATA READY/DATA OUTPUT (DRDY/DOUT)
The digital output pin on the ADS1245 serves two
purposes. It indicates when new data is ready by going
low. Afterwards, on the first rising edge of SCLK, the
DRDY/DOUT pin changes function and begins outputting
the conversion data, MSB first. Data is shifted out on each
0
9.6
19.2
Frequency (kHz)
Figure 18. Frequency Response
8
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