Direct
Input
–15VDC
21
22
28
+5VDC
30
19
R2
5kΩ
24
25
1µF
1µF
Analog
Common
+
+
22
+
1µF
R1
5kΩ
Comp
In
27
26
Digital
Common
6.3kΩ
From D/A
Converter
+15VDC
Comparator
to Logic
VREF
Bipolar
Offset
FIGURE 8. Recommended Power Supply Decoupling.
FIGURE 9. ADC71 Input Scaling Circuit.
LAYOUT AND OPERATING INSTRUCTIONS
Layout Precautions
OPTIONAL EXTERNAL GAIN
AND OFFSET ADJUSTMENTS
Analog and digital common are not connected internally in
the ADC71 but should be connected together as close to the
unit as possible, preferably to a large plane under the ADC.
If these grounds must be run separately, use wide conductor
patterns and a 0.01µF to 0.1µF non-polarized bypass capaci-
tor between analog and digital commons at the unit. Low
impedance analog and digital commons returns are essential
for low noise performance. Coupling between analog inputs
and digital lines should be minimized by careful layout. The
comparator input (Pin 27) is extremely sensitive to noise.
Any connection to this point should be as short as possible
and shielded by Analog Common patterns.
Gain and Offset errors may be trimmed to zero using
external gain and offset trim potentiometers connected to the
ADC as shown in Figure 6 and 7. Multiturn potentiometers
with 100ppm/°C or better TCRs are recommended for mini-
mum drift over temperature and time. These pots may be any
value from 10kΩ to 100kΩ. All resistors should be 20%
carbon or better. Pin 29 (Gain Adjust) and Pin 27 (Offset
Adjust) may be left open of no external adjustment is
required.
ADJUSTMENT PROCEDURE
OFFSET — Connect the Offset potentiometer (make sure R1
is as close to pin 27 as possible) as shown in Figure 6. Sweep
the input through the end point transition voltage that should
cause an output transition to all bits Off (EIN).
POWER SUPPLY DECOUPLING
The power supplies should be bypassed with tantalum ca-
pacitors as shown in Figure 8 to obtain noise free operation.
These capacitors should be located close to the ADC.
Adjust the Offset potentiometer until the actual end point
transition voltage occurs at EIN. The ideal transition voltage
values of the input are given in Table I.
INPUT SCALING
The analog input should be scaled as close to the maximum
input signal range as possible in order to utilize the maxi-
mum signal resolution of the A/D converter. Connect the
input signal as shown in Table II. See Figure 9 for circuit
details.
GAIN — Connect the Gain Adjust potentiometer as shown
in Figure 7. Sweep the input through the end point transition
voltage that should cause an output transition to all bits on
(EIN). Adjust the Gain potentiometer until the actual end
point transition voltage occurs at EIN.
Table I details the transition voltage levels required.
CONNECT
INPUT
SIGNAL
RANGE
CONNECT
PIN 26
TO PIN
CONNECT
PIN 24
TO
INPUT
SIGNAL
TO PIN
CONVERT COMMAND CONSIDERATIONS
OUTPUT
CODE
Convert command resets the converter whenever taken high.
This insures a valid conversion on the first conversion after
power-up.
±10V
±5V
±2.5V
0 to +5V
0 to +10V
0 to +20V
COB or CTC(1)
COB or CTC(1)
COB or CTC(1)
CSB
27
27
27
22
22
22
Input Signal
Open
Pin 27
Pin 27
Open
24
25
25
25
25
24
Convert command must stay low during a conversion unless
it is desired to reset the converter during a conversion.
CSB
CSB
Input Signal
NOTE: (1) Obtained by inverting MSB pin 1.
ADDITIONAL CONNECTIONS REQUIRED
The ADC71 may be operated at faster speeds by connecting
the Short-Cycle Input, pin 32, as shown in Table III. Conver-
sion speeds, linearity, and resolutions are shown for refer-
ence.
TABLE II. ADC71 Input Scaling Connections.
®
7
ADC71
BB [ BURR-BROWN CORPORATION ]
