0.01µF(1)
MSB
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Offset
Adjust
Convert Command From
Control Logic
Dotted Lines
Are External
Connections
+5VDC
3
270kΩ
1.8MΩ
4
+15VDC
5
+
Gain
10kΩ to
6
1µF
1µF
100kΩ
Bipolar
Offset
Adjust
7
10kΩ to
100kΩ
ADC71
8
Analog Input
±10V
9
NC
10
11
12
13
14
15
16
+
–15VDC
+
1µF
Digital
Common
Analog
Common
Status Output to
Control Logic
NC
NC
NOTE: (1) Capacitor should be connected even if external gain adjust is not used.
FIGURE 5. ADC71 Connections for: ±10V Analog Input, 14-Bit Resolution (Short-Cycled), Parallel Data Output.
SERIAL DATA
Two straight binary (complementary) codes are available on
the serial output line: CSB and COB. The serial data is
available only during conversion and appears with MSB
+15VDC
(a)
1.8MΩ
27
10kΩ to 100kΩ
Offset Adjust
occurring first. The serial data is synchronous with the
internal clock as shown in the timing diagrams of Figures 2
and 3. The LSB and transition values shown in Table I also
apply to the serial data output except for the CTC code.
Comparator In
–15VDC
+15VDC
(b)
180kΩ
180kΩ
22kΩ
DISCUSSION
OF SPECIFICATIONS
The ADC71 is specified to provide critical performance
criteria for a wide variety of applications. The most critical
specifications for an A/D converter are linearity, drift, gain
and offset errors. This ADC is factory-trimmed and tested
for all critical key specifications.
27
10kΩ to 100kΩ
Offset Adjust
Comparator In
–15VDC
FIGURE 6. Two Methods of Connecting Optional Offset
Adjust with a 0.4% of FSR of Adjustment.
GAIN AND OFFSET ERROR
+15VDC
Initial Gain and Offset errors are factory-trimmed to typi-
cally ±0.1% of FSR (typically ±0.05% for unipolar offset) at
25°C. These errors may be trimmed to zero by connecting
external trim potentiometers as shown in Figures 6 and 7.
270kΩ
29
10kΩ to 100kΩ
Gain Adjust
Gain Adjust
0.01µF
–15VDC
22
POWER SUPPLY SENSITIVITY
Analog Common
Changes in the DC power supplies will affect accuracy. The
power supply sensitivity is specified for ±0.003% of FSR/
%∆VS for ±15V supplies and ±0.001% of FSR/%∆S for +5
supplies. Normally, regulated power supplies with 1% or
less ripple are recommended for use with this ADC. See
Layout Precautions, Power Supply Decoupling and Figure
8.
FIGURE 7. Connecting Optional Gain Adjust with a 0.2%
Range of Adjustment.
®
ADC71
6
BB [ BURR-BROWN CORPORATION ]
