TYPICAL PERFORMANCE CURVES
At +25°C and rated power supplies unless otherwise noted.
POWER SUPPLY REJECTION
vs SUPPLY RIPPLE FREQUENCY
GAIN DRIFT ERROR (% OF FSR)
vs TEMPERATURE
+0.10
0.1
0.06
+0.08
ADC71AG, BG
0.04
–15VDC
+0.06
ADC71JG,KG
+0.04
0.02
+0.02
0
0.01
0.006
0.004
+15VDC
–0.02
–0.04
–0.06
–0.08
–0.10
+5VDC
0.002
0.001
–25°C
0°C
+25°C
+70°C +85°C
1
10
100
1k
10k
100k
Temperature (°C)
Frequency (Hz)
NOTE: Pa g es 4 &5
w ere sw it ch ed fo r
Ab rid g ed Versio n
fo r '9 6 d a t a b o o k.
DISCUSSION OF
PERFORMANCE
The accuracy of a successive approximation A/D converter
is described by the transfer function shown in Figure 1. All
successive approximation A/D converters have an inherent
Quantization Error of ±1/2 LSB. The remaining errors in the
A/D converter are combinations of analog errors due to the
linear circuitry, matching and tracking properties of the
ladder and scaling networks, power supply rejection, and
reference errors. In summary, these errors consist of initial
errors including Gain, Offset, Linearity, Differential Linear-
ity, and Power Supply Sensitivity. Initial Gain and Offset
errors may be adjusted to zero. Gain drift over temperature
rotates the line (Figure 1) about the zero or minus full scale
point (all bits Off) and Offset drift shifts the line left or right
over the operating temperature range. Linearity error is
unadjustable and is the most meaningful indicator of A/D
converter accuracy. Linearity error is the deviation of an
actual bit transition from the ideal transition value at any
level over the range of the A/D converter. A Differential
Linearity error of ±1/2 LSB means that the width of each bit
step over the range of the A/D converter is 1 LSB, ±1/2 LSB.
The ADC71 is monotonic, assuring that the output digital
code either increases or remains the same for increasing
analog input signals. Burr-Brown guarantees that these con-
verters will have no missing codes over a specified tempera-
ture range when short-cycled for 14-bit operation.
TIMING CONSIDERATIONS
The timing diagram (Figure 2) assumes an analog input such
that the positive true digital word 1001 1000 1001 0110
exists. The output will be complementary as shown in Figure
2 (0110 0111 0110 1001 is the digital output). Figures 3 and
4 are timing diagrams showing the relationship of serial data
to clock and valid data to status.
All Bits On
0000 ... 0000
Gain
Error
0000 ... 0001
0111 ... 1101
0111 ... 1110
0111 ... 1111
1000 ... 0000
1000 ... 0001
1111 ... 1110
1111 ... 1111
DEFINITION OF DIGITAL CODES
–1/2LSB
Parallel Data
Two binary codes are available on the ADC71 parallel
output; they are complementary (logic “0” is true) straight
binary (CSB) for unipolar input signal ranges and comple-
mentary offset binary (COB) for bipolar input signal ranges.
Complementary two’s complement (CTC) may be obtained
by inverting MSB (Pin 1).
+1/2LSB
Offset
Error
eIN On
All Bits Off
Analog Input
+FSR/2–1LSB
–FSR/2
Table I shows the LSB, transition values, and code defini-
tions for each possible analog input signal range for 12-, 13-
and 14-bit resolutions. Figure 5 shows the connections for
14-bit resolution, parallel data output, with ±10V input.
eIN Off
NOTE: (1) See Table I for Digital Code Definitions.
FIGURE 1. Input vs Output for an Ideal Bipolar A/D
Converter.
®
5
ADC71
BB [ BURR-BROWN CORPORATION ]
