2Gb DDR2 - AS4C256M8D2
Signal Pin Description
Pin
CK, CK
CKE
Type
Input
Input
Function
The system clock input. All inputs except DQs and DMs are sampled on the rising edge of CK.
Activates the CK signal when high and deactivates the CK signal when low, thereby initiates either the
Power Down mode, or the Self Refresh mode.
CS
Input
Input
Input
CS enables the command decoder when low and disables the command decoder when high. When
the command decoder is disabled, new commands are ignored but previous operations continue.
RAS, CAS, WE
A0 - A14
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be
executed by the SDRAM.
During a Bank Activate command cycle, A0-A14 defines the row address (RA0-RA14) when sampled
at the rising clock edge for x8.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn) when sampled
at the rising clock edge.CAn depends on the SDRAM organization:
256M x 8 DDR CAn = CA9
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation at the end of
the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1, BA2 defines the
bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0, BA1and BA2 to control
which bank(s) to precharge. If A10 is high, all eight banks will be precharged simultaneously regardless
of state of BA0 , BA1 and BA2.
BA0-BA2
DQx
Input
Selects which bank is to be active.
Input/
Data Input/Output pins operate in the same manner as on conventional DRAMs.
DQ0-DQ7 for x8 device.
Output
DQS, (DQS)
Input/
Data Strobe, output with read data, input with write data. Edge-aligned with read data, centered in write
data. For x8 device, an RDQS option using DM pin can be enabled via the EMRS(1) to simplify read
timing. The data strobes DQS and RDQS may be used in single ended mode or paired with optional
complimentary signals DQS and RDQS to provide differential pair signaling to the system during both
reads and writes. An EMRS(1) control bit enables or disables all complementary data strobe signals.
RDQS, (RDQS)
Output
DM
Input
DM is an input mask signal for write data. Input data is masked when DM is sampled high along with
that input data during a Write access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading is designed to match that of DQ and DQS pins.
For x8 device, the function of DM or RDQS/RDQS is enabled by EMRS command.
VDD, VSS
VDDQ, VSSQ
VREF
Supply
Supply
Input
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise immunity.
SSTL Reference Voltage for Inputs
VDDL, VSSDL
ODT
Supply
Input
Isolated power supply and ground for the DLL to provide improved noise immunity.
On Die Termination Enable. It enables termination resistance internal to the DRAM. ODT is applied to
each DQ, DQS, DQS, RDQS, RDQS and DM for x8 device. ODT will be ignored if EMRS disable the
function.
Confidential
-4/70-
Rev.1.0 Sep. 2015
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
