2Gb DDR2 - AS4C256M8D2
Features
Description
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High speed data transfer rates with system frequency up to
400 MHz
The AS4C256M8D2 is a eight bank DDR DRAM organized as
8 banks x 32Mbit x 8. The AS4C256M8D2 achieves high
speed data transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output data
to a system clock.
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8 internal banks for concurrent operation
4-bit prefetch architecture
Programmable CAS Latency: 3, 4 ,5 , 6 and 7
Programmable Additive Latency:0, 1, 2, 3 , 4, 5 and 6
Write Latency = Read Latency -1
Programmable Wrap Sequence: Sequential or Interleave
Programmable Burst Length: 4 and 8
Automatic and Controlled Precharge Command
Power Down Mode
The chip is designed to comply with the following key DDR2
SDRAM features:(1) posted CAS with additive latency, (2) write
latency = read latency-1, (3) On Die Termination.
All of the control, address, circuits are synchronized with the
positive edge of an externally supplied clock. I/O s are synchro-
nized with a pair of bidirectional strobes (DQS, DQS) in a source
synchronous fashion.
Auto Refresh and Self Refresh
Refresh Interval: 7.8 us at -40oC ≤ Tcase ≤ 85oC,
Operating the eight memory banks in an interleaved fashion
allows random access operation to occur at a higher rate than is
possible with standard DRAMs. A sequential and gapless data
rate is possible depending on burst length, CAS latency and
speed grade of the device.
3.9 us at 85oC < Tcase ≤ 105oC
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ODT (On-Die Termination)
Weak Strength Data-Output Driver Option
Bidirectional differential Data Strobe (Single-ended data-
strobe is an optional feature)
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On-Chip DLL aligns DQ and DQs transitions with CK transi-
tions
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DQS can be disabled for single-ended data strobe
Read Data Strobe (RDQS) supported (x8 only)
Differential clock inputs CK and CK
JEDEC Power Supply 1.8V ± 0.1V
VDDQ =1.8V ± 0.1V
Available in 60-ball FBGA for x8 component
RoHS compliant
tRAS lockout supported
Table 1:
Table 1. Speed Grade Information
Speed Grade
Clock Frequency CAS Latency
tRCD
tRP
(ns)
(ns)
DDR2-800
400 MHz
5
12.5
12.5
Table 2. Ordering Information
Product part No Org
Temperature
Package
AS4C256M8D2-25BCN 256M x 8
AS4C256M8D2-25BIN 256M x 8
Commercial (Extended)
0°C to +95°C
Industrial
60-ball FBGA
60-ball FBGA
-40°C to +95°C (Extended)
Confidential
-2/70-
Rev.1.0 Sep. 2015
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
