2Gb DDR2 - AS4C256M8D2
13. The DDR2 SDRAM is now ready for normal operation.
*1) To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin.
Initialization Sequence after Power Up
tCHtCL
CK
/CK
tIS
CKE
ODT
ANY
CMD
PRE
ALL
PRE
ALL
NOP
EMRS
DLL
MRS
REF
MRS
EMRS
REF
Command
EMRS
tRFC
tRP
tMRD
tRFC
tMRD
tMRD
400ns
tRP
Enable OCD
Defaults
min. 200 Cycle
OCD
EXIT
DLL
RESET
OCD
Default
ENABLE
Programming the Mode Register
For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time (tWR) are user
defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable func-
tion, driver impedance, additive CAS latency, single-ended strobe and ODT (On Die Termination) are also user defined
variables and must be programmed with an Extended Mode Register Set (EMRS) command. Contents of the Mode
Register (MR) or Extended Mode Registers (EMR(#)) can be altered by re-executing the MRS and EMRS Commands.
If the user chooses to modify only a subset of the MRS or EMRS variables, all variables must be redefined when the
MRS or EMRS commands are issued.
MRS, EMRS and Reset DLL do not affect array contents, which means reinitialization including those can be executed
any time after power-up without affecting array contents.
Confidential
-7/70-
Rev.1.0 Sep. 2015
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
