2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation.
AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM)
ASTM Standard F1192 -
Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by
Heavy Ion Irradiation of Semiconductor Devices.
(Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor
Drive, West Conshohocken, PA 19428-2959; http://www.astm.org.)
ELECTRONICS INDUSTRIES ALLIANCE (EIA)
JEDEC Standard EIA/JESD51 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
JEDEC Standard EIA/JESD78 - IC Latch-Up Test.
ANSI/TIA/EIA Standard EIA-644 - Electrical Characteristics of Low-Voltage Differential Signaling (LVDS) Interface Circuits
J-STD-002
Solderability Tests for Component Leads, Terminations, Lugs, Terminals and Wires
(Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA
22201; http://www.jedec.org.)
INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS (IEEE)
IEEE Standard 1149.1 - Test Access Port and Boundary-Scan Architecture
(Applications for copies should be addressed to the IEEE, 1828 L Street, N.W., Suite 1202, Washington, D.C. 20036-5104.)
stds-info@ieee.org
(Non-Government standards and other publications are normally available from the organizations that prepare or distribute the
documents. These documents also may be available in or through libraries or other informational services.)
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1.
3.2.1.1 Case outlines X, Y, Z, U, M, T, and N assembly. Case outlines X, Y, Z, U, M, T, and N are assembled with die
attachment (Silver filled Cyanate Ester material), wire bond (25.4m (1.0 mil) aluminum wire), and hermetic sealed with AuSn lid
preformed.
3.2.1.2 Bonding pads. Devices built with all case outlines have two rows of bonding pads on the silicon side with 95 micron
bond pad pitch and are bonded on multi-tiered packages. Wire bonds from adjacent bond pads on the silicon may be seen on
top view as crossing with each other; however, they are connected to different tiers on the package and have different wire loop
heights. In any case, all wires still maintain a minimum clearance of two wire diameters in any direction from the adjacent wires.
SIZE
STANDARD
5962-04221
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
SHEET
C
6
DSCC FORM 2234
APR 97
ACTEL [ Actel Corporation ]
