1.4 Recommended operating conditions.
1.5V core supply voltage ........................................................................................... 1.425 to 1.575 V dc
1.5V I/O supply voltage .............................................................................................. 1.425 to 1.575 V dc
1.8V I/O supply voltage .............................................................................................. 1.71 to 1.89 V dc
2.5V I/O supply voltage .............................................................................................. 2.375 to 2.625 V dc
3.3V I/O supply voltage .............................................................................................. 3.0 to 3.6 V dc
2.5V V
3.3V V
3.3V V
I/O supply voltage (no differential I/O used) .......................................... 2.375 to 2.625 V dc
I/O supply voltage (differential or voltage referenced I/O used) ............ 3.0 to 3.6 V dc
supply voltage range ............................................................................. 3.0 to 3.6 V dc
CCDA
CCDA
PUMP
Junction operating temperature range (T ) ................................................................ -55oC to +125oC
J
1.5 Power-Up/Down Sequence. All device I/Os are tri-stated during power-up until normal device operating conditions are
reached, which is when I/Os enter user mode. V
, V
CCA CCI
, and V
can be powered up or powered down in any sequence.
CCDA
All device I/Os are hot-swap compliant with cold-sparing support (except PCI).
1.5.1 R-cells and I/O Registers. On a chip-wide basis at power-up, all R-cells and I/O Registers are either cleared or preset
by driving the global clear (GCLR) and global preset (GPSET) inputs (see Figure 3). Default setting is to clear all registers
(GCLR = 0 and GPSET =1) at device power-up.
1.6 Device Logic Configuration.
1.6.1 Core array logics include two types of logic modules: the register cell (R-cell) and the combinatorial cell (C-cell). C-cell
contains carry logic for efficient arithmetic functions. R-cell appears as a single D-type flip-flop to user, but is implemented in
silicon with triple module redundancy (TMR) to improve SEU performance. Each TMR R-cell consist of three master-slave latch
pairs, each with asynchronous self-correcting feedback paths. Output of the TMR R-cell is the result of the majority voting of the
outputs of the three flip flops in the TMR R-cells. Logic modules are grouped as SuperCluster, each SuperCluster has two
Clusters, and each Cluster includes two C-cells, one R-cell, two transmit (TX) and two receive (RX) routing buffers. Each
SuperCluster also includes an independent buffer module. On the chip level, SuperClusters are organized into core tiles, which
are arrayed to build up the full chip. There are 16 core tiles in this device and each tile has 336 SuperClusters, resulting a total
of 10,752 R-cells and 21,504 C-cells in the device.
1.6.2 Clock Resources are available with two types of global clock networks throughout the chip. There are four dedicated
hardwired clock input pins (HCLKA/B/C/D) that will directly drive all the sequential modules (R-cells, I/O registers, embedded
RAM/FIFO). There are also four global clock input pins (CLKE/F/G/H) for routed clock distribution networks that are buffered
prior to clocking the R-cells; the routed clocks can also be programmed to drive S0, S1, PSET, and CLR of a register, or as the
inputs of any C-cell. Input levels for all clocks are compatible with all supported I/O standards (there is a P/N pin pair to support
differential I/O standards). All clock networks have been hardened to improve SEU performance.
1.6.3 Embedded RAM is available as a global resource. There are four 4,608-bit RAM blocks in each tile, with a total of
294,912 bits in the device. Each 4,608-bit RAM block can be organized as 128x36, 256x18, 512x9, 1,024x4, 2,048x2, or 4,096
x1 (Depth x Word in bits), and are cascadable to create larger memory sizes. Each RAM block has independent read and write
ports, which enables simultaneous read and write operations; it also contains its own embedded FIFO controller, allowing the
RAM blocks to be configured as either RAM or FIFO. SRAM structures are susceptible to radiation upsets, to achieve high level
SEU performance; manufacturer has provided an IP core to enhance the SEU tolerance of the embedded RAM blocks by
mitigating upsets with Error Detection and Correction (EDAC) and background memory-refresher (or scrubber). Registers in the
FIFO controller are not hardened for radiation, so when high SEU tolerance is required, the FIFO control unit should be
implemented with core logic. Note: Simultaneous read and write operations to the same address is not supported.
SIZE
STANDARD
5962-04221
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
SHEET
C
4
DSCC FORM 2234
APR 97
ACTEL [ Actel Corporation ]
