VS1005g Datasheet
10 VS1005 PERIPHERALS AND REGISTERS
10.10.3 Nand Flash Interface
Nand Flash Controller Registers
Reg Type Reset Abbrev
Description
0xFC77
0xFC78
0xFC79
0xFC7A
r/w
r/w
r/w
r/w
0
0
0
0
NF_CONF Nand flash configuration register
NF_CF
NF_PNTR Nand flash memory pointer
NF_LEN Nand flash data length register (bytes)
Nand flash control register
NF_CONF Bits
Bits Description
Name
NF_CONF_SCKM
NF_CONF_SLV
NF_CONF_FLT
NF_CONF_IENA
NF_CONF_WS
9
8
7
6
Slave mode clock active edge select
Slave mode enable
Nand flash output bus float enable
Nand flash interface interrupt enable
5:0 Nand flash interface clock configuration
NF_CONF_SCKM selects slave mode active clock edge. If set the data bus is read at rising
edge of ready/busy line, when reset at falling edge.
NF_CONF_SLV configures the nand flash interface to slave input mode. In slave mode the nand
flash interface reads data from 8-bit bus and stores it to memory. The clock is the ready/bysy
input.
NF_CONF_FLT leaves the data output bus (flash input bus) floating when set. When reset the
bus is driven to low or high state.
NF_CONF_IENA enables the nand flash interrupt request when set.
NF_CONF_WS configures the length of nand flash read enable and write enable pulses. The
cycle time is 2 x (NF_CONF_WS + 1) dsp clock cycles.
NF_CF Bits
Name
Bits Description
NF_CF_RDY
4
2
1
0
Status of nand flash ready line
NF_CF_RDWRX
NF_CF_ENA
NF_CF_DBUF
Read (1) or write (0) select
Start nand flash read or write
Use peripheral memory
NF_CF_RDY register is monitoring the current state of nand flash ready/busy line. The line has
pull-up and when it is in its low state the flash chip is busy.
NF_CF_RDWRX is a read or write select. When this register is set the operation is a nand flash
read. When reset the nand flash interface writes to flash.
NF_CF_ENA starts nand flash read or write when set. When all bytes are transfered this
register is reset and an interrupt request is generated.
NF_CF_DBUF configures nand flash interface to use peripheral memory when set. If NF_CF_DBUF
is reset when nand flash interface is enabled, the data is read from DSPI_IDATA register or writ-
ten to DSPI_ODATA register. This is a one byte transaction and big endian format is used.
Version: 0.2, 2012-03-16
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ETC [ ETC ]
