Power Driver Integrated Full Digital Audio Amplifier
NTP-8230
100
101
PWM3A is connected to PWM port 3B
PWM3B is connected to PWM port 3B
Addr 0x38: Miscellaneous PWM Control
Bit
7
6
5
4
3
2
1
0
Name
X
X
X
POL
BHL
AHL
MD
Name
MD
Description
PWM output mode
Value
b’00
b‟01
b‟10
b‟11
b’0
b‟1
b’0
b‟1
Meaning
Ref.
AD mode with asynchronous signal pair
AD mode with synchronous signal pair
PWM D-BTL MODE (see 0x4E)
AM Interference mode
Low
High
Low
High
AHL
BHL
POL
A-out state
When switching off
B-out state
when switching off
Ch3 polarity Control b’0
Normal
Inverse
b‟1
Addr 0x39: I2C Glitch filter
Bit
7
6
5
4
3
2
1
0
Name
GFO
DUR
Name
DUR
Description
glitch width
Value
Meaning
Ref.
b‟0000000 minimum pulse width = DUR + 20 ns
reset default = 15 * 10 ns (DUR default =
b‟1111111 b’0001111)
~
GFO
Glitch filter
enable/disable
b’0
b‟1
Glitch filter on
Bypass
Addr 0x3A : Headphone Mute Control
Bit
7
6
5
4
3
2
1
0
Name
X
X
X
X
X
X
X
HP_MUTE
Name
Description
Value
Meaning
Ref.
HP_MUTE Use this register to
mute external
b’0
Default. External headphone is muted by
active low signal
headphone
b‟1
External headphone is muted by active
high signal.
Reserved addr 0x3B~0x49
Addr 0x4A : SE Soft Start Control 0
Bit
7
6
5
4
3
2
1
0
Name
X
X
X
X
X
X
X
SSE
Name
SSE
Description
SE_STE
Value
b’0
b‟1
Meaning
Ref.
SE Soft Start Disable (SE Normal Start)
SE Soft Start Enable
Copyright ⓒ NeoFidelity, Inc.
Page 38
Document Number: DS8230 draft ver. 0.1
2011-01-11
ETC [ ETC ]
