80C186XL/80C188XL
functions as in compatible mode, and may be pro-
grammed for activity with ready logic and wait states
accordingly. As in Compatible Mode, MCS2 will func-
tion for one-fourth a programmed block size.
DRAM Refresh Control Unit
The Refresh Control Unit (RCU) automatically gen-
erates DRAM refresh bus cycles. The RCU operates
only in Enhanced Mode. After a programmable peri-
od of time, the RCU generates a memory read re-
quest to the BIU. If the address generated during a
refresh bus cycle is within the range of a properly
programmed chip select, that chip select will be acti-
vated when the BIU executes the refresh bus cycle.
Table 1. MCS Assignments
Compatible
Enhanced Mode
Mode
MCS0
MCS1
MCS2
MCS3
PEREQ Processor Extension Request
ERROR NPX Error
MCS2 Mid-Range Chip Select
Power-Save Control
NPS
Numeric Processor Select
The 80C186XL, when in Enhanced Mode, can enter
a power saving state by internally dividing the proc-
essor clock frequency by a programmable factor.
This divided frequency is also available at the
CLKOUT pin.
ONCE Test Mode
To facilitate testing and inspection of devices when
fixed into a target system, the 80C186XL has a test
mode available which allows all pins to be placed in
a high-impedance state. ONCE stands for ‘‘ON Cir-
cuit Emulation’’. When placed in this mode, the
80C186XL will put all pins in the high-impedance
state until RESET.
All internal logic, including the Refresh Control Unit
and the timers, have their clocks slowed down by
the division factor. To maintain a real time count or a
fixed DRAM refresh rate, these peripherals must be
re-programmed when entering and leaving the pow-
er-save mode.
The ONCE mode is selected by tying the UCS and
the LCS LOW during RESET. These pins are sam-
pled on the low-to-high transition of the RES pin.
The UCS and the LCS pins have weak internal pull-
up resistors similar to the RD and TEST/BUSY pins
to guarantee ONCE Mode is not entered inadver-
tently during normal operation. LCS and UCS must
be held low at least one clock after RES goes high
to guarantee entrance into ONCE Mode.
Interface for 80C187 Math
Coprocessor (80C186XL Only)
In Enhanced Mode, three of the mid-range memory
chip selects are redefined according to Table 1 for
use with the 80C187. The fourth chip select, MCS2
7
ETC [ ETC ]
