80C186XL/80C188XL
The 80C186XL provides a chip select for low memo-
ry called LCS. The bottom of memory contains the
interrupt vector table, starting at location 00000H.
mum of 8 clocks), one cycle to fetch data and the
other to store data.
The 80C186XL provides four MCS lines which are
active within a user-locatable memory block. This
block can be located within the 80C186XL 1 Mbyte
memory address space exclusive of the areas de-
fined by UCS and LCS. Both the base address and
size of this memory block are programmable.
Timer/Counter Unit
The 80C186XL provides three internal 16-bit pro-
grammable timers. Two of these are highly flexible
and are connected to four external pins (2 per timer).
They can be used to count external events, time ex-
ternal events, generate nonrepetitive waveforms,
etc. The third timer is not connected to any external
pins, and is useful for real-time coding and time de-
lay applications. In addition, the third timer can be
used as a prescaler to the other two, or as a DMA
request source.
The 80C186XL can generate chip selects for up to
seven peripheral devices. These chip selects are ac-
tive for seven contiguous blocks of 128 bytes above
a programmable base address. The base address
may be located in either memory or I/O space.
The 80C186XL can generate a READY signal inter-
nally for each of the memory or peripheral CS lines.
The number of WAIT states to be inserted for each
peripheral or memory is programmable to provide
0–3 wait states for all accesses to the area for
which the chip select is active. In addition, the
80C186XL may be programmed to either ignore ex-
ternal READY for each chip-select range individually
or to factor external READY with the integrated
ready generator.
Interrupt Control Unit
The 80C186XL can receive interrupts from a number
of sources, both internal and external. The
80C186XL has 5 external and 2 internal interrupt
sources (Timer/Couners and DMA). The internal in-
terrupt controller serves to merge these requests on
a priority basis, for individual service by the CPU.
Enhanced Mode Operation
Upon RESET, the Chip-Select/Ready Logic will per-
form the following actions:
In Compatible Mode the 80C186XL operates with all
the features of the NMOS 80186, with the exception
of 8087 support (i.e. no math coprocessing is possi-
ble in Compatible Mode). Queue-Status information
is still available for design purposes other than 8087
support.
All chip-select outputs will be driven HIGH.
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Upon leaving RESET, the UCS line will be pro-
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grammed to provide chip selects to a 1K block
with the accompanying READY control bits set at
011 to insert 3 wait states in conjunction with ex-
ternal READY (i.e., UMCS resets to FFFBH).
All the Enhanced Mode features are completely
masked when in Compatible Mode. A write to any of
the Enhanced Mode registers will have no effect,
while a read will not return any valid data.
No other chip select or READY control registers
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have any predefined values after RESET. They
will not become active until the CPU accesses
their control registers.
In Enhanced Mode, the 80C186XL will operate with
Power-Save, DRAM refresh, and numerics coproc-
essor support (80C186XL only) in addition to all the
Compatible Mode features.
DMA Unit
The 80C186XL DMA controller provides two inde-
pendent high-speed DMA channels. Data transfers
can occur between memory and I/O spaces (e.g.,
Memory to I/O) or within the same space (e.g.,
Memory to Memory or I/O to I/O). Data can be
transferred either in bytes (8 bits) or in words (16
bits) to or from even or odd addresses.
If connected to a math coprocessor (80C186XL
only), this mode will be invoked automatically. With-
out an NPX, this mode can be entered by tying the
RESET output signal from the 80C186XL to the
TEST/BUSY input.
NOTE:
Only byte transfers are possible on the 80C188XL.
Queue-Status Mode
The queue-status mode is entered by strapping the
RD pin low. RD is sampled at RESET and if LOW,
the 80C186XL will reconfigure the ALE and WR pins
to be QS0 and QS1 respectively. This mode is avail-
able on the 80C186XL in both Compatible and En-
hanced Modes.
Each DMA channel maintains both a 20-bit source
and destination pointer which can be optionally in-
cremented or decremented after each data transfer
(by one or two depending on byte or word transfers).
Each data transfer consumes 2 bus cycles (a mini-
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ETC [ ETC ]
