80C186XL/80C188XL
Table 3. Pin Descriptions (Continued)
Pin
Pin
Input
Output
States
Pin Description
Name
Type
Type
TMR IN 0
TMR IN 1
I
A(L)
A(E)
Timer Inputs are used either as clock or control signals,
depending upon the programmed timer mode. These
inputs are active HIGH (or LOW-to-HIGH transitions are
counted) and internally synchronized. Timer Inputs must
be tied HIGH when not being used as clock or retrigger
inputs.
TMR OUT 0
TMR OUT 1
O
I
H(Q)
R(1)
Timer outputs are used to provide single pulse or
continuous waveform generation, depending upon the
timer mode selected. These outputs are not floated
during a bus hold.
DRQ0
DRQ1
A(L)
A(E)
DMA Request is asserted HIGH by an external device
when it is ready for DMA Channel 0 or 1 to perform a
transfer. These signals are level-triggered and internally
synchronized.
NMI
I
The Non-Maskable Interrupt input causes a Type 2
interrupt. An NMI transition from LOW to HIGH is
latched and synchronized internally, and initiates the
interrupt at the next instruction boundary. NMI must be
asserted for at least one CLKOUT period. The Non-
Maskable Interrupt cannot be avoided by programming.
INT0
INT1/SELECT
I
A(E)
A(L)
Maskable Interrupt Requests can be requested by
activating one of these pins. When configured as inputs,
these pins are active HIGH. Interrupt Requests are
synchronized internally. INT2 and INT3 may be
configured to provide active-LOW interrupt-
INT2/INTA0
INT3/INTA1/IRQ
I/O
A(E)
A(L)
H(1)
R(Z)
acknowledge output signals. All interrupt inputs may be
configured to be either edge- or level-triggered. To
ensure recognition, all interrupt requests must remain
active until the interrupt is acknowledged. When Slave
Mode is selected, the function of these pins changes
(see Interrupt Controller section of this data sheet).
A19/S6
A18/S5
A17/S4
A16/S3
(A8–A15)
O
H(Z)
R(Z)
Address Bus Outputs and Bus Cycle Status (3–6)
indicate the four most significant address bits during T .
These signals are active HIGH.
1
During T , T , T and T , the S6 pin is LOW to indicate
W
2
3
4
a CPU-initiated bus cycle or HIGH to indicate a DMA-
initiated or refresh bus cycle. During the same T-states,
S3, S4 and S5 are always LOW. On the 80C188XL,
A15–A8 provide valid address information for the entire
bus cycle.
AD0–AD15
(AD0–AD7)
I/O
S(L)
H(Z)
R(Z)
Address/Data Bus signals constitute the time
multiplexed memory or I/O address (T ) and data (T ,
1
T , T and T ) bus. The bus is active HIGH. For the
2
3
W
4
80C186XL, A is analogous to BHE for the lower byte of
0
the data bus, pins D through D . It is LOW during T
7
0
1
when a byte is to be transferred onto the lower portion
of the bus in memory or I/O operations.
NOTE:
Pin names in parentheses apply to the 80C188XL.
11
ETC [ ETC ]
