80C186XL/80C188XL
16-Bit High-Integration Embedded Processors
CONTENTS
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CONTENTS
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INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4
AC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24
Major Cycle Timings (Read Cycle) ÀÀÀÀÀÀÀÀÀ 24
Major Cycle Timings (Write Cycle) ÀÀÀÀÀÀÀÀÀ 26
80C186XL CORE ARCHITECTURE ÀÀÀÀÀÀÀÀ 4
80C186XL Clock Generator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4
Bus Interface Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5
Major Cycle Timings (Interrupt
Acknowledge Cycle) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 27
Software Halt Cycle Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 28
Clock Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 29
80C186XL PERIPHERAL
ARCHITECTURE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5
Chip-Select/Ready Generation Logic ÀÀÀÀÀÀÀ 5
DMA Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6
Timer/Counter Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6
Interrupt Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6
Enhanced Mode Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6
Queue-Status Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6
DRAM Refresh Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
Power-Save Control ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
Ready, Peripheral and Queue Status
Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30
Reset and Hold/HLDA Timings ÀÀÀÀÀÀÀÀÀÀÀÀ 31
AC TIMING WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36
AC CHARACTERISTICS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37
EXPLANATION OF THE AC
SYMBOLS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 39
Interface for 80C187 Math Coprocessor
(80C186XL Only) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
DERATING CURVES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40
80C186XL/80C188XL EXPRESS ÀÀÀÀÀÀÀÀÀ 41
ONCE Test Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
80C186XL/80C188XL EXECUTION
TIMINGS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41
PACKAGE INFORMATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
Pin Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
INSTRUCTION SET SUMMARY ÀÀÀÀÀÀÀÀÀÀ 42
REVISION HISTORY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 48
ERRATA ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 48
PRODUCT IDENTIFICATION ÀÀÀÀÀÀÀÀÀÀÀÀÀ 48
80C186XL/80C188XL Pinout
Diagrams ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16
ELECTRICAL SPECIFICATIONS ÀÀÀÀÀÀÀÀÀ 22
Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22
DC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22
Power Supply Current ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23
2
ETC [ ETC ]
