24LC16B
FIGURE 7-1:
CURRENT ADDRESS READ
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
DATA n
SDA LINE
S
A
C
K
N
O
A
C
K
P
BUS ACTIVITY
FIGURE 7-2:
RANDOM READ
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS (n)
CONTROL
BYTE
DATA (n)
S
SDA LINE
A
C
K
A
C
K
S
A
C
K
N
O
A
C
K
P
BUS ACTIVITY
FIGURE 7-3:
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
SEQUENTIAL READ
CONTROL
BYTE
DATA n
DATA n + 1
DATA n + 2
DATA n + X
S
T
O
P
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
8.0
8.1
PIN DESCRIPTIONS
SDA Serial Address/Data Input/
Output
8.3
WP
This pin must be connected to either V
SS
or V
CC
.
If tied to Vss normal memory operation is enabled
(read/write the entire memory 000-7FF).
If tied to V
CC
, WRITE operations are inhibited. The
entire memory will be write-protected. Read operations
are not affected.
This feature allows the user to use the 24LC16B as a
serial ROM when WP is enabled (tied to V
CC
).
This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to V
CC
(typical 10KΩ for 100 kHz, 2 KΩ for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
8.4
A0, A1, A2
8.2
SCL Serial Clock
These pins are not used by the 24LC16B. They may
be left floating or tied to either V
SS
or V
CC
.
This input is used to synchronize the data transfer from
and to the device.
©
1998 Microchip Technology Inc.
DS20070H-page 7
ETC [ ETC ]
