24LC16B
TABLE 1-3:
AC CHARACTERISTICS
STANDARD
MODE
Min
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
—
4000
4700
—
—
4000
4700
0
250
4000
—
4700
Max
100
—
—
1000
300
—
—
—
—
—
3500
—
Vcc = 4.5V - 5.5V
FAST MODE
Min
—
600
1300
—
—
600
600
0
100
600
—
1300
Max
400
—
—
300
300
—
—
—
—
—
900
—
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Symbol
Units
Remarks
START condition setup time T
SU
:
STA
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
(Note 1)
(Note 1)
After this period the first
clock pulse is generated
Only relevant for repeated
START condition
Output fall time from V
IH
min to V
IL
max
Input filter spike suppres-
sion (SDA and SCL pins)
Write cycle time
Endurance
T
OF
T
SP
T
WR
—
—
—
—
1M
250
50
10
—
20 +0.1
C
B
—
—
1M
250
50
10
—
ns
ns
(Note 2)
Time the bus must be free
before a new transmission
can start
(Note 1), C
B
≤
100 pF
(Note 3)
ms
Byte or Page mode
cycles 25°C, Vcc = 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. C
B
= total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a T
I
specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on our website.
FIGURE 1-2:
BUS TIMING DATA
T
F
T
HIGH
T
LOW
T
R
SCL
T
SU
:
STA
T
HD
:
DAT
T
HD
:
STA
T
SP
T
AA
T
BUF
T
SU
:
DAT
T
SU
:
STO
SCL
IN
T
AA
T
HD
:
STA
SCL
OUT
©
1998 Microchip Technology Inc.
DS20070H-page 3
ETC [ ETC ]
