EM351 / EM357
Pin # Signal
Direction
Description
JTMS
I
JTAG mode select from debugger
Selected when in JTAG mode (default mode)
JTAG mode is enabled after power-up or by forcing nRESET low
Select Serial Wire mode using the ARM-defined protocol through a
debugger
Internal pull-up is enabled
SWDIO
I/O
Serial Wire bidirectional data to/from debugger
Enable Serial Wire mode (see JTMS description)
Select Serial Wire mode using the ARM-defined protocol through a
debugger
Internal pull-up is enabled
36
PB0
I/O
Digital I/O
VREF
Analog O
ADC reference output
Enable analog function with GPIO_PBCFGL[3:0]
VREF
Analog I
ADC reference input
Enable analog function with GPIO_PBCFGL[3:0]
Enable reference output with an Ember system function
IRQA
I
External interrupt source A
TRACECLK
O
Synchronous CPU trace clock
Enable trace interface in ARM core
(see also Pin 25)
Select alternate output function with GPIO_PBCFGL[3:0]
TIM1CLK
TIM2MSK
VDD_PADS
PC1
I
Timer 1 external clock input
Timer 2 external clock mask input
Pads supply (2.1-3.6 V)
Digital I/O
I
37
38
Power
I/O
ADC3
Analog
ADC Input 3
Enable analog function with GPIO_PCCFGL[7:4]
SWO
O
Serial Wire Output asynchronous trace output to debugger
Select asynchronous trace interface in ARM core
Enable trace interface in ARM core
(see also Pin 33)
Select alternate output function with GPIO_PCCFGL[7:4]
TRACEDATA0
O
Synchronous CPU trace data bit 0
Select 1-, 2- or 4-wire synchronous trace interface in ARM core
Enable trace interface in ARM core
Select alternate output function with GPIO_PCCFGL[7:4]
39
40
VDD_MEM
PC0
Power
1.8 V supply (flash, RAM)
I/O
Digital I/O
High
current
Either enable with GPIO_DBGCFG[5],
or enable Serial Wire mode (see JTMS description, Pin 35) and disable
TRACEDATA1
JRST
I
I
JTAG reset input from debugger
Selected when in JTAG mode (default mode, see JTMS description) and
TRACEDATA1 is disabled
Internal pull-up is enabled
IRQD1
Default external interrupt source D
1-8
120-035X-000D
Preliminary
ETC [ ETC ]
