ADM7008
Register Description
4.3.11 PHY 100M Module Control Register (Register 12h)
Bit # Name Description
15:8 Reserved
SELFX
Type Default
Interface
RO
0h
7
R/W
pin ~PI_SELTP
Fiber Select
1: Fiber Mode
0: TP Mode
6:5 Reserved
R/W
R/W
1h
4
DISSCR
pin When
Disable Scrambler
programmed to
fiber mode, set to
1 automatically
1: Disable Scrambler
0: Enable Scrambler
When set to fiber mode, this bit will be
forced to 1 automatically. Write 0 to this
bit in Fiber Mode has no effect.
3
ENFEFI
R/W
pin ~DISFEFI
OR ed result of
ENFEFI and
FTPREN
Enable FEFI
1: Enable FEFI
0: Disable FEFI
2
1
0
Reserved
Reserved
Reserved
RO
0h
R/W
R/W
1h
0h
4.3.12 LED Configuration Register (Register 13h)
Bit #
Name Description
Type Default
Interface
15:14 Reserved
RO
RO
0h
13:12 BLINK_T
00 REC_BLINK_T
10/100M Blink Timer Select.
Value 10M Blink Time 100M Blink
Time
M
M
00
01
10
11
100 ms
200 ms
400 ms
100 ms
100 ms
100 ms
100 ms
50 ms
11:8 LNKCTRL
RO 1010 REC_LNKLED_
CTRL
Link/Act LED Control.
0000: Collision
0001: All Errors
0010: Duplex
0011: Duplex/Collision
0100: Speed
0101: Link
0110: Transmit Activity
0111: Receive Activity
1000: TX/RX Activity
1001: Link/Receive Activity
ADMtek Inc.
4-13
ETC [ ETC ]
