ADM7008
Function Description
Automatic “Signal_Detect” Function Block
Due to pin limitation, ADM7008 doesn’t support SDP/SDN in fiber mode, which is used
to connect to fiber transceiver to indicate there is signal on the fiber. Instead, ADM7008
use the data on RXP/RXN to detect consecutive 65 “1” on the receive data (Recovered
from RXP/RXN) to determine whether “Signal” is detected or not. When the detect
condition is true (Consecutive 65 bits “1”), internal signal detect signal will be asserted to
inform receive relative blocks to be ready for coming receive activities.
3.1.5 100Base-FX Transmitter
In 100Base FX transmit, the serial data stream is driven out as NRZI PECL signals,
which enters fiber transceiver in differential-pairs form. Fiber transceiver should be
available working at 3.3V environment.
3.1.6 10Base-T Module
The 10Base-T Transceiver Module is IEEE 802.3 compliant. It includes the receiver,
transmitter, collision, heartbeat, loopback, jabber, waveshaper, and link integrity
functions, as defined in the standard. Figure 5 provides an overview for the 10Base-T
module.
The ADM7008 10Base-T module is comprised of the following functional blocks:
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Manchester encoder and decoder
Collision detector
Link test function
Transmit driver and receiver
Serial and parallel interface
Jabber and SQE test functions
Polarity detection and correction
3.1.7 Operation Modes
The ADM7008 10Base-T module is capable of operating in either half-duplex mode or
full-duplex mode. In half-duplex mode, the ADM7008 functions as an IEEE 802.3
compliant transceiver with fully integrated filtering. The COL signal is asserted during
collisions or jabber events, and the CRS signal is asserted during transmit and receive. In
full duplex mode the ADM7008 can simultaneously transmit and receive data.
3.1.8 Manchester Encoder/Decoder
Data encoding and transmission begins when the transmission enable input (TXEN) goes
high and continues as long as the transceiver is in good link state. Transmission ends
when the transmission enable input goes low. The last transition occurs at the center of
the bit cell if the last bit is a 1, or at the boundary of the bit cell if the last bit is 0.
A differential input receiver circuit accomplishes decoding and a phase-locked loop that
separate the Manchester-encoded data stream into clock signals and NRZ data. The
decoder detects the end of a frame when no more midbit transitions are detected. Within
one and half bit times after the last bit, carrier sense is deasserted.
ADMtek Inc.
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