欢迎访问ic37.com |
会员登录 免费注册
发布采购

ADM7008 参数 Datasheet PDF下载

ADM7008图片预览
型号: ADM7008
PDF下载: 下载PDF文件 查看货源
内容描述: 八以太网10 / 100M PHY [Octal Ethernet 10/100M PHY]
分类和应用: 外围集成电路数据传输以太网局域网(LAN)标准时钟
文件页数/大小: 92 页 / 2746 K
品牌: ETC [ ETC ]
 浏览型号ADM7008的Datasheet PDF文件第35页浏览型号ADM7008的Datasheet PDF文件第36页浏览型号ADM7008的Datasheet PDF文件第37页浏览型号ADM7008的Datasheet PDF文件第38页浏览型号ADM7008的Datasheet PDF文件第40页浏览型号ADM7008的Datasheet PDF文件第41页浏览型号ADM7008的Datasheet PDF文件第42页浏览型号ADM7008的Datasheet PDF文件第43页  
ADM7008  
Function Description  
3.1.9 Transmit Driver and Receiver  
The ADM7008 integrates all the required signal conditioning functions in its 10Base-T  
block such that external filters are not required. Only one isolation transformer and  
impedance matching resistors are needed for the 10Base-T transmit and receive interface.  
The internal transmit filtering ensures that all the harmonics in the transmission signal are  
attenuated properly.  
3.1.10 Smart Squelch  
The smart squelch circuit is responsible for determining when valid data is present on the  
differential receive. The ADM7008 implements an intelligent receive squelch on the  
RXP/RXN differential inputs to ensure that impulse noise on the receive inputs will not  
be mistaken for a valid signal. The squelch circuitry employs a combination of amplitude  
and timing measurements (as specified in the IEEE 802.3 10Base-T standard) to  
determine the validity of data on the twisted-pair inputs.  
The signal at the start of the packet is checked by the analog squelch circuit and any  
pulses not exceeding the squelch level (either positive or negative, depending upon  
polarity) will be rejected. Once this first squelch level is overcome correctly, the  
opposite squelch level must then be exceeded within 150ns. Finally, the signal must  
exceed the original squelch level within an additional 150ns to ensure that the input  
waveform will not be rejected.  
Only after all these conditions have been satisfied will a control signal be generated to  
indicate to the remainder of the circuitry that valid data is present.  
Valid data is considered to be present until the squelch level has not been generated for a  
time longer than 200 ns, indicating end of packet. Once good data has been detected, the  
squelch levels are reduced to minimize the effect of noise, causing premature end-of-  
packet detection. The receive squelch threshold level can be lowered for use in longer  
cable applications. This is achieved by setting bit 7 of register address 10h.  
3.1.11 Carrier Sense  
Carrier Sense (CRS) is asserted due to receive activity once valid data is detected via the  
smart squelch function. For 10 Mbps half duplex operation, CRS is asserted during either  
packet transmission or reception. For 10 Mbps full duplex and repeater mode operations,  
the CRS is asserted only due to receive activity.85  
ADMtek Inc.  
3-9  
 
 复制成功!