ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
9.6.10.2 DMA
The transfer of the last byte of a DMA data block
will be followed by a DMA End Of Block transmit or
receive interrupt, setting the TXEOB or RXEOB
bit.
Two DMA channels are associated with the SCI,
for transmit and for receive. These follow the reg-
ister scheme as described in the DMA chapter.
A typical Transmission End Of Block interrupt rou-
tine will perform the following actions:
DMA Reception
To perform a DMA transfer in reception mode:
1. Restore the DMA counter register (TDCPR).
2. Restore the DMA address register (TDAPR).
1. Initialize the DMA counter (RDCPR) and DMA
address (RDAPR) registers
3. Clear the Transmitter Shift Register Empty bit
TXSEM in the S_ISR register to avoid spurious
interrupts.
2. Enable DMA by setting the RXD bit in the IDPR
register.
3. DMA transfer is started when data is received
by the SCI.
4. Clear the Transmitter End Of Block (TXEOB)
pending bit in the IMR register.
5. Set the TXD bit in the IDPR register to enable
DMA.
DMA Transmission
To perform a DMA transfer in transmission mode:
6. Load the Transmitter Buffer Register (TXBR)
with the next byte to transmit.
1. Initialize the DMA counter (TDCPR) and DMA
address (TDAPR) registers.
The above procedure handles the case where a
further DMA transfer is to be performed.
2. Enable DMA by setting the TXD bit in the IDPR
register.
3. DMA transfer is started by writing a byte in the
Transmitter Buffer register (TXBR).
Error Interrupt Handling
If an error interrupt occurs while DMA is enabled in
reception mode, DMA transfer is stopped.
If this byte is the first data byte to be transmitted,
the DMA counter and address registers must be
initialized to begin DMA transmission at the sec-
ond byte. Alternatively, DMA transfer can be start-
ed by writing a dummy byte in the TXBR register.
To resume DMA transfer, the error interrupt han-
dling routine must clear the corresponding error
flag. In the case of an Overrun error, the routine
must also read the RXBR register.
DMA Interrupts
When DMA is active, the Received Data Pending
and the Transmitter Shift Register Empty interrupt
sources are replaced by the DMA End Of Block re-
ceive and transmit interrupt sources.
Character Search Mode with DMA
In Character Search Mode with DMA, when a
character match occurs, this character is not trans-
ferred. DMA continues with the next received char-
acter. To avoid an Overrun error occurring, the
Character Match interrupt service routine must
read the RXBR register.
Note: To handle DMA transfer correctly in trans-
mission, the BSN bit in the IMR register must be
cleared. This selects the Transmitter Shift Register
Empty event as the DMA interrupt source.
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