ST6200C/ST6201C/ST6203C
11.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for V , f
, and T .
DD OSC
A
11.5.1 General Timings
1)
Symbol
Parameter
Conditions
Min
2
Typ
4
Max
5
Unit
tCPU
µs
t
Instruction cycle time
c(INST)
f
f
=8MHz
3.25
6
6.5
8.125
11
CPU
2)
tCPU
µs
Interrupt reaction time
t
v(IT)
t
= ∆t
+ 6
=8MHz
9.75
17.875
v(IT)
c(INST)
CPU
11.5.2 External Clock Source
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
OSC input pin high level voltage
0.7xV
V
V
DD
OSCINH
IN
DD
V
V
OSC input pin low level voltage
0.3xV
DD
OSCINL
IN
SS
t
t
3)
w(OSCINH)
see Figure 49
OSC high or low time
IN
w(OSCINL)
ns
t
t
3)
r(OSCIN)
OSC rise or fall time
IN
f(OSCIN)
I
OSCx Input leakage current
V
≤V ≤V
DD
± 2
µA
L
SS IN
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
3. Data based on design simulation and/or technology characteristics, not tested in production.
Figure 49. Typical Application with an External Clock Source
90%
V
OSCINH
10%
V
OSCINL
t
t
w(OSCINH)
t
t
w(OSCINL)
f(OSCIN)
r(OSCIN)
OSC
OSC
OUT
Not connected
f
OSC
EXTERNAL
CLOCK SOURCE
I
L
IN
ST62XX
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ETC [ ETC ]
