T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
Table 3. LXT350 Signal Descriptions (Continued)
Pin #
Symbol
I/O1
Description
PLCC
QFP
Tristate.
HARDWARE MODES:
Connect TRSTE High to force all output pins to the high impedance state.
TRSTE, in conjunction with the MODE pin, selects the operating modes listed
in Table 5 on page 19.
9
7
TRSTE
DI
HOST MODES:
Connect TRSTE High to force all output pins to the high-impedance state.
Connect this pin Low for normal operation.
HARDWARE MODES:
Jitter Attenuation Select. Selects jitter attenuation location:
Setting JASEL High activates the jitter attenuator in the receive path.
Setting JASEL Low activates the jitter attenuator in the transmit path.
Setting JASEL to Midrange2 disables jitter attenuation.
11
10
JASEL
DI
HOST MODES:
Connect Low in Host mode.
Loss of Signal Indicator. LOS goes High upon receipt of 175 consecutive
spaces and returns Low when the received signal reaches a mark density of
12.5% (determined by receipt of 16 marks within a sliding window of 128 bits
with fewer than 100 consecutive zeros). Note that the transceiver outputs
received marks on RPOS and RNEG even when LOS is High.
12
13
LOS / QPD
DO
AO
QRSS Pattern Detect. In QRSS mode, QPD stays High until the transceiver
detects a QRSS pattern. When a QRSS pattern is detected, the pin goes Low.
Any bit errors cause QPD to go High for half a clock cycle. This output can be
used to trigger an external error counter. Note that a LOS condition will cause
QPD to remain High. See Figure 11.
Transmit Tip and Ring. Differential driver output pair designed to drive a 50 -
200 Ω load. The transformer and line matching resistors should be selected to
give the desired pulse height and return loss performance. See “Application
Information” on page 33.
13
16
15
19
TTIP
TRING
14
15
17
16
18
20
TGND
TVCC
GND
-
-
-
Ground return for the transmit driver power supply TVCC.
+5 VDC Power Supply for the transmit drivers. TVCC must not vary from VCC
by more than ± 0.3 V.
Tie to Ground.
Receive Tip and Ring. The Alternate Mark Inversion (AMI) signal received
from the line is applied at these pins. A 1:1 transformer is required. Data and
clock recovered from RTIP/RRING are output on the RPOS/RNEG (or RDATA
in Unipolar mode), and RCLK pins.
19
20
24
25
RTIP
AI
RRING
+5 VDC Power Supply for all circuits except the transmit drivers. Transmit
drivers are supplied by TVCC.
21
22
27
29
VCC
GND
-
-
Ground return for power supply VCC.
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output.
2. Midrange is a voltage level such that 2.3 V ≤ Midrange ≤ 2.7 V. Midrange may also be established by letting the pin float.
Datasheet
11
ETC [ ETC ]
