IP1001 LF
Data Sheet
Pin description (continued)
Pin no.
Label
Type
Description
Configuration
50,51,53,7,8 PHY_ADDR[4:0] LI/O,
IPH
PHY Address Configuration
These pins are latched upon power-on reset to define the
PHY address of IP1001.
PHY_ADDR[1:0] are internally pulled high.
PHY_ADDR[4:0] share the same pins with RXD6, RXD7,
RX_ER, CRS and COL.
36
48
RGMII_N/GMII IPL
RXPHASE_SEL LI/O
GMII (MII)/ RGMII MAC Interface Mode Selection
This pin is latched upon power-on reset to define the
RGMII/GMII interface mode.
0: RGMII mode (default)
1: GMII/MII mode
RX_CLK Phase Selection
This pin is latched upon power-on reset, and acts as the initial
value of register16 [0] to adjust timing of RX_CLK.
0: No output delay is added on RX_CLK
1: An output delay is added on RX_CLK (with respect to RXD,
about 2ns delay in 1000BASE-T, and about 4ns delay in
100BASE-TX and 10BASE-T).
RXPHASE_SEL shares the same pin with RXD4.
49
TXPHASE_SEL LI/O
GTX_CLK/TXC Phase Selection
This pin is latched upon power-on reset, and acts as the initial
value of register16 [1] to adjust timing of GTX_CLK/TXC.
0: No input delay is added on GTX_CLK/TXC
1: An input delay is added on GTX_CLK/TXC (with respect to
TXD, about 2ns delay in 1000BASE-T, and about 4ns
delay in 100BASE-TX and 10BASE-T).
TXPHASE_SEL shares the same pin with RXD5.
6/48
Dec. 18, 2007
IP1001-DS-R06
Copyright © 2006, IC Plus Corp.
ETC [ ETC ]
