IP1001 LF
Data Sheet
4
Register Descriptions
Abbreviation description
Abbreviation
SC
Description
Self-Clear
LH
Latched High
LL
Latched Low
RO
Read Only
R/W
Read and Write
Not Affected
NA
HW Reset
SW Reset
Reset by RESET# pin
Reset by MII register 0 bit 15
PHY registers
The IP1001 supports a full set of PHY registers, which can be accessed through the MDC/MDIO interface.
Register
Reg0
Description
Control Register
Reg1
Status Register
Reg2
PHY Identifier Register
Reg3
PHY Identifier Register
Reg4
Auto-Negotiation advertise register
Link Partner Ability Register
Auto-Negotiation Expansion Register
Auto-Negotiation Next Page Transmit Register
Auto-Negotiation Link Partner Next Page Register
1000BASE-T Control Register
1000BASE-T Status Register
Reserved. Do not access to these registers.
Extended Status Register
Reg5
Reg6
Reg7
Reg8
Reg9
Reg10
Reg11~14
Reg15
Reg16
Reg17
Reg18~19
Reg20
Reg21~31
PHY Specific Control Register1
PHY Link Status Register
Reserved. Do not access to these registers.
PHY Specific Control Register2
Reserved
26/48
Dec. 18, 2007
IP1001-DS-R06
Copyright © 2006, IC Plus Corp.
ETC [ ETC ]
