Data Sheet
June 1999
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 48. Series 2 Master Serial Configuration Mode Timing Characteristics
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA/B Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA/B Industrial: VDD = 3.0 V to 3.6 V,
–40 °C ≤ TA ≤ +85 °C.
Parameter
DIN Setup Time
Symbol
TS
Min
60.0
0
Nom
—
Max
—
Unit
ns
DIN Hold Time
TH
—
—
ns
CCLK Frequency (M3 = 0)
CCLK Frequency (M3 = 1)
CCLK to DOUT Delay
FC
3.8
0.48
—
10.0
1.25
—
15.2
1.9
30
MHz
MHz
ns
FC
TD
Note: Serial configuration data is transmitted out on DOUT on the falling edge of CCLK after it is input DIN.
CCLK
TS
TH
BIT N
DIN
TD
DOUT
BIT N
5-4532(F)
Figure 66. Master Serial Configuration Mode Timing Diagram
Lucent Technologies Inc.
161
ETC [ ETC ]
